公开(公告)号：US20130179645A1

公开(公告)日：2013-07-11

申请号：US13344941

申请日：2012-01-06

Applicant: Hisato Matsuo ,  Rika Nagahara ,  Scott J. Schaffer

Inventor： Hisato Matsuo ,  Rika Nagahara ,  Scott J. Schaffer

IPC: G06F12/00

CPC classification number: G06F9/544 ,  G06F12/00 ,  G06F15/167

Abstract: A method for equalizing the bandwidth of requesters using a shared memory system is disclosed. In one embodiment, such a method includes receiving multiple access requests to access a shared memory system. Each access request originates from a different requester coupled to the shared memory system. The method then determines which of the access requests has been waiting the longest to access the shared memory system. The access requests are then ordered so that the access request that has been waiting the longest is transmitted to the shared memory system after the other access requests. The requester associated with the longest-waiting access request may then transmit additional access requests to the shared memory system immediately after the longest-waiting access request has been transmitted. A corresponding apparatus and computer program product are also disclosed.

Abstract translation: 公开了一种使用共享存储器系统来均衡使用者带宽的方法。 在一个实施例中，这种方法包括接收访问共享存储器系统的多个访问请求。 每个访问请求源自耦合到共享存储器系统的不同请求者。 该方法然后确定哪个访问请求已经等待最长时间访问共享存储器系统。 然后对访问请求进行排序，使得等待最长的访问请求在其他访问请求之后被传送到共享存储器系统。 与最长等待的访问请求相关联的请求者然后可以在发送最长等待的访问请求之后立即向附加存储器系统发送附加访问请求。 还公开了相应的装置和计算机程序产品。

公开(公告)号：US09268721B2

公开(公告)日：2016-02-23

申请号：US13989743

申请日：2011-10-06

Applicant: Hisato Matsuo ,  Rika Nagahara ,  Kenji Ohtani

Inventor： Hisato Matsuo ,  Rika Nagahara ,  Kenji Ohtani

IPC: G06F3/00 ,  G06F13/00 ,  G06F13/16

CPC classification number: G11C7/1048 ,  G06F13/1642 ,  G06F13/1647 ,  G06F13/1663 ,  G06F13/4234 ,  G11C7/1072

Abstract: The present invention includes a plurality of CPUs using memory as main memory, another function block using memory as a buffer, a CPU interface which controls access transfer from the plurality of CPUs to memory, and a DRAM controller for performing arbitration of the access transfer to the memory. Therein, the CPU interface causes access requests from the plurality of CPUs to wait, and receives and stores the address, data transfer mode and data size of each access, notifies the DRAM controller of the access requests, and then, upon receiving grant signals for the access requests, sends information to the DRAM controller according to the grant signals, whereupon the DRAM controller receives the grant signals, and on the basis of the access arbitration, specifies CPUs for which transfers have been granted so as to send the grant signals to the CPU interface.

Abstract translation: 本发明包括使用存储器作为主存储器的多个CPU，使用存储器作为缓冲器的另一功能块，控制从多个CPU到存储器的访问传输的CPU接口，以及用于执行访问转移的仲裁的DRAM控制器 记忆。 其中，CPU接口使得来自多个CPU的访问请求等待，并且接收并存储每个访问的地址，数据传输模式和数据大小，向DRAM控制器通知访问请求，然后在接收到 访问请求根据授权信号向DRAM控制器发送信息，于是DRAM控制器接收授权信号，并且基于访问仲裁，指定已经被授权传输的CPU，以便将授权信号发送到 CPU接口。

公开(公告)号：US09208002B2

公开(公告)日：2015-12-08

申请号：US13344941

申请日：2012-01-06

Applicant: Hisato Matsuo ,  Rika Nagahara ,  Scott Jeffrey Schaffer

Inventor： Hisato Matsuo ,  Rika Nagahara ,  Scott Jeffrey Schaffer

IPC: G06F12/00 ,  G06F9/54 ,  G06F15/167

CPC classification number: G06F9/544 ,  G06F12/00 ,  G06F15/167

Abstract: A method for equalizing the bandwidth of requesters using a shared memory system is disclosed. In one embodiment, such a method includes receiving multiple access requests to access a shared memory system. Each access request originates from a different requester coupled to the shared memory system. The method then determines which of the access requests has been waiting the longest to access the shared memory system. The access requests are then ordered so that the access request that has been waiting the longest is transmitted to the shared memory system after the other access requests. The requester associated with the longest-waiting access request may then transmit additional access requests to the shared memory system immediately after the longest-waiting access request has been transmitted. A corresponding apparatus and computer program product are also disclosed.

Abstract translation: 公开了一种使用共享存储器系统来均衡使用者带宽的方法。 在一个实施例中，这种方法包括接收访问共享存储器系统的多个访问请求。 每个访问请求源自耦合到共享存储器系统的不同请求者。 该方法然后确定哪个访问请求已经等待最长时间访问共享存储器系统。 然后对访问请求进行排序，使得等待最长的访问请求在其他访问请求之后被传送到共享存储器系统。 与最长等待的访问请求相关联的请求者然后可以在发送最长等待的访问请求之后立即向附加存储器系统发送附加访问请求。 还公开了相应的装置和计算机程序产品。

公开(公告)号：US20140059286A1

公开(公告)日：2014-02-27

申请号：US13989743

申请日：2011-10-06

Applicant: Hisato Matsuo ,  Rika Nagahara ,  Kenji Ohtani

Inventor： Hisato Matsuo ,  Rika Nagahara ,  Kenji Ohtani

IPC: G06F13/16

CPC classification number: G11C7/1048 ,  G06F13/1642 ,  G06F13/1647 ,  G06F13/1663 ,  G06F13/4234 ,  G11C7/1072

Abstract: Provided is a memory access device for a shared memory mechanism of main memory for a plurality of CPUs. The present invention includes a plurality of CPUs using memory as main memory, another function block using memory as a buffer, a CPU interface which controls access transfer from the plurality of CPUs to memory, and a DRAM controller for performing arbitration of the access transfer to the memory. Therein, the CPU interface causes access requests from the plurality of CPUs to wait, and receives and stores the address, data transfer mode and data size of each access, notifies the DRAM controller of the access requests, and then, upon receiving grant signals for the access requests, sends information to the DRAM controller according to the grant signals, whereupon the DRAM controller receives the grant signals, and on the basis of the access arbitration, specifies CPUs for which transfers have been granted so as to send the grant signals to the CPU interface.

Abstract translation: 提供了一种用于多个CPU的主存储器的共享存储器机构的存储器访问装置。 本发明包括使用存储器作为主存储器的多个CPU，使用存储器作为缓冲器的另一功能块，控制从多个CPU到存储器的访问传输的CPU接口，以及用于执行访问转移的仲裁的DRAM控制器 记忆。 其中，CPU接口使得来自多个CPU的访问请求等待，并且接收并存储每个访问的地址，数据传输模式和数据大小，向DRAM控制器通知访问请求，然后在接收到 访问请求根据授权信号向DRAM控制器发送信息，于是DRAM控制器接收授权信号，并且基于访问仲裁，指定已经被授权传输的CPU，以便将授权信号发送到 CPU接口。