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    Translating between an ethernet protocol and a converged enhanced ethernet protocol
    11.
    发明授权
    Translating between an ethernet protocol and a converged enhanced ethernet protocol 有权
    在以太网协议和融合增强型以太网协议之间进行转换

    公开(公告)号：US08902750B2

    公开(公告)日：2014-12-02

    申请号：US13150507

    申请日：2011-06-01

    申请人： Claude Basso ,  Anil Pothireddy ,  Christoph Raisch ,  Saravanan Sethuraman ,  Vibhor K. Srivastava ,  Jan-Bernd Themann ,  Fabrice J. Verplanken

    发明人： Claude Basso ,  Anil Pothireddy ,  Christoph Raisch ,  Saravanan Sethuraman ,  Vibhor K. Srivastava ,  Jan-Bernd Themann ,  Fabrice J. Verplanken

    IPC分类号： H04L12/801 ,  H04L12/26 ,  H04L29/06 ,  H04L12/823 ,  H04L12/835

    CPC分类号： H04L47/10 ,  H04L47/17 ,  H04L47/30 ,  H04L47/32 ,  H04L47/34 ,  H04L69/08

    摘要： Translating between an Ethernet protocol used by a first network component and a Converged Enhanced Ethernet (CEE) protocol used by a second network component, the first and second components coupled through a CEE Converter that translates by: for data flow from the first network component to the second network component: receiving, by the CEE converter, traffic flow definition parameters for a single CEE protocol data flow; calculating, by a credit manager, available buffer space in an outbound frame buffer of the CEE converter for the data flow; communicating, by the credit manager to a CEE credit driver of the first component, the calculated size of the buffer space together with a start sequence number and a flow identifier; and responding, by the CEE credit driver to the CEE converter, with Ethernet frames comprising a private header that includes the flow identifier and a sequence number.

    摘要翻译： 在由第一网络组件使用的以太网协议和第二网络组件使用的融合增强以太网（CEE）协议之间进行转换，所述第一和第二组件通过CEE转换器耦合，所述CEE转换器通过以下方式耦合：用于从第一网络组件到 第二网络组件：由CEE转换器接收单个CEE协议数据流的业务流定义参数; 由信用管理器计算用于数据流的CEE转换器的出站帧缓冲器中的可用缓冲器空间; 由信用管理器将第一组件的CEE信用驱动程序与计算出的缓冲区空间的大小以及起始序列号和流标识符进行通信; 并由CEE信用驱动程序向CEE转换器响应包括包含流标识符和序列号的专用报头的以太网帧。

    HASH COLLISION REDUCTION SYSTEM
    12.
    发明申请
    HASH COLLISION REDUCTION SYSTEM 有权
    HASH碰撞减少系统

    公开(公告)号：US20130311492A1

    公开(公告)日：2013-11-21

    申请号：US13475990

    申请日：2012-05-20

    申请人： Jean L. Calvignac ,  Casimer M. DeCusatis ,  Fabrice J. Verplanken ,  Daniel Wind

    发明人： Jean L. Calvignac ,  Casimer M. DeCusatis ,  Fabrice J. Verplanken ,  Daniel Wind

    IPC分类号： G06F17/30

    CPC分类号： G06F17/30002 ,  G06F17/30949 ,  H04L9/00 ,  H04L9/3236 ,  H04L45/7453

    摘要： An improved computer system that can include a controller having a computer processor, the controller to reduce insertion times and/or collisions when interfacing with new components introduced to the controller. The system may also include a collision avoidance apparatus that reduces hashing collisions by using a plurality of tables and a plurality of keys per bucket. The system may further include a hash apparatus in communication with the controller to map the plurality of keys to the plurality of tables where the hash apparatus uses a single hash logic to provide an avalanche effect when one key is changed which results in nearly half of bits changing in the plurality of tables.

    摘要翻译： 一种改进的计算机系统，其可以包括具有计算机处理器的控制器，所述控制器在与引入到控制器的新组件接口时减少插入时间和/或冲突。 该系统还可以包括通过使用多个表和每个桶的多个密钥来减少散列冲突的冲突避免装置。 该系统还可以包括与控制器通信的散列装置，以将多个密钥映射到多个表，其中散列装置使用单个散列逻辑以在一个密钥改变时提供雪崩效应，这导致几乎一半的比特 改变多个表。

    Providing to a Parser and Processors in a Network Processor Access to an External Coprocessor
    14.
    发明申请
    Providing to a Parser and Processors in a Network Processor Access to an External Coprocessor 有权
    提供给网络处理器中的解析器和处理器访问外部协处理器

    公开(公告)号：US20120204002A1

    公开(公告)日：2012-08-09

    申请号：US13365679

    申请日：2012-02-03

    申请人： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Natarajan Vaidhyanathan ,  Fabrice J. Verplanken ,  Colin B. Verrilli

    发明人： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Natarajan Vaidhyanathan ,  Fabrice J. Verplanken ,  Colin B. Verrilli

    IPC分类号： G06F15/76 ,  G06F9/06

    CPC分类号： H04L69/12

    摘要： A mechanism is provided for sharing a communication used by a parser (parser path) in a network adapter of a network processor for sending requests for a process to be executed by an external coprocessor. The parser path is shared by processors of the network processor (software path) to send requests to the external processor. The mechanism uses for the software path a request mailbox comprising a control address and a data field accessed by MMIO for sending two types of messages, one message type to read or write resources and one message type to trigger an external process in the coprocessor and a response mailbox for receiving response from the external coprocessor comprising a data field and a flag field. The other processors of the network poll the flag until set and get the coprocessor result in the data field.

    摘要翻译： 提供了一种用于共享由网络处理器的网络适配器中的解析器（解析器路径）使用的通信的机制，用于发送对要由外部协处理器执行的进程的请求。 解析器路径由网络处理器（软件路径）的处理器共享，以将请求发送到外部处理器。 该机制用于软件路径，包括由MMIO访问的控制地址和数据字段的请求邮箱，用于发送两种类型的消息，一种用于读取或写入资源的消息类型和一个消息类型以触发协处理器中的外部进程， 用于从包括数据字段和标志字段的外部协处理器接收响应的响应邮箱。 网络的其他处理器轮询该标志直到设置，并获得协处理器结果的数据字段。

    Translating Between An Ethernet Protocol And A Converged Enhanced Ethernet Protocol
    17.
    发明申请
    Translating Between An Ethernet Protocol And A Converged Enhanced Ethernet Protocol 有权
    在以太网协议和融合增强以太网协议之间进行翻译

    公开(公告)号：US20110299394A1

    公开(公告)日：2011-12-08

    申请号：US13150507

    申请日：2011-06-01

    申请人： Claude Basso ,  Anil Pothireddy ,  Christoph Raisch ,  Saravanan Sethuraman ,  Vibhor K. Srivastava ,  Jan-Bernd Themann ,  Fabrice J. Verplanken

    发明人： Claude Basso ,  Anil Pothireddy ,  Christoph Raisch ,  Saravanan Sethuraman ,  Vibhor K. Srivastava ,  Jan-Bernd Themann ,  Fabrice J. Verplanken

    IPC分类号： H04L12/26

    CPC分类号： H04L47/10 ,  H04L47/17 ,  H04L47/30 ,  H04L47/32 ,  H04L47/34 ,  H04L69/08

    摘要： Translating between an Ethernet protocol used by a first network component and a Converged Enhanced Ethernet (CEE) protocol used by a second network component, the first and second components coupled through a CEE Converter that translates by: for data flow from the first network component to the second network component: receiving, by the CEE converter, traffic flow definition parameters for a single CEE protocol data flow; calculating, by a credit manager, available buffer space in an outbound frame buffer of the CEE converter for the data flow; communicating, by the credit manager to a CEE credit driver of the first component, the calculated size of the buffer space together with a start sequence number and a flow identifier; and responding, by the CEE credit driver to the CEE converter, with Ethernet frames comprising a private header that includes the flow identifier and a sequence number.

    摘要翻译： 在由第一网络组件使用的以太网协议和第二网络组件使用的融合增强以太网（CEE）协议之间进行转换，所述第一和第二组件通过CEE转换器耦合，所述CEE转换器通过以下方式耦合：用于从第一网络组件到 第二网络组件：由CEE转换器接收单个CEE协议数据流的业务流定义参数; 由信用管理器计算用于数据流的CEE转换器的出站帧缓冲器中的可用缓冲器空间; 由信用管理器将第一组件的CEE信用驱动程序与计算出的缓冲区空间的大小以及起始序列号和流标识符进行通信; 并由CEE信用驱动程序向CEE转换器响应包括包含流标识符和序列号的专用报头的以太网帧。

    Assignment Constraint Matrix for Assigning Work From Multiple Sources to Multiple Sinks
    18.
    发明申请
    Assignment Constraint Matrix for Assigning Work From Multiple Sources to Multiple Sinks 失效
    分配约束矩阵用于将工作从多个来源分配到多个接收器

    公开(公告)号：US20110158249A1

    公开(公告)日：2011-06-30

    申请号：US12650080

    申请日：2009-12-30

    申请人： Claude Basso ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Hubertus Franke ,  Fabrice J. Verplanken ,  Colin B. Verrilli

    发明人： Claude Basso ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Hubertus Franke ,  Fabrice J. Verplanken ,  Colin B. Verrilli

    IPC分类号： H04L12/56

    CPC分类号： H04L49/9047

    摘要： An assignment constraint matrix method and apparatus used in assigning work, such as data packets, from a plurality of sources, such as data queues in a network processing device, to a plurality of sinks, such as processor threads in the network processing device. The assignment constraint matrix is implemented as a plurality of qualifier matrixes adapted to operate simultaneously in parallel. Each of the plurality of qualifier matrixes is adapted to determine sources in a subset of supported sources that are qualified to provide work to a set of sinks based on assignment constraints. The determination of qualified sources may be based sink availability information that may be provided for a set of sinks on a single chip or distributed on multiple chips.

    摘要翻译： 一种分配约束矩阵方法和装置，用于从网络处理设备中的多个源（诸如网络处理设备中的数据队列）将诸如数据分组的工作分配给诸如网络处理设备中的处理器线程的多个接收器。 分配约束矩阵被实现为适于同时并行操作的多个限定符矩阵。 多个限定符矩阵中的每一个适于确定被支持的源的子集中的源，所述源被限定为基于分配约束向一组接收器提供工作。 合格来源的确定可以是可以在单个芯片上提供用于一组接收器或分布在多个芯片上的接收器可用性信息。

    Data path for data extraction from streaming data
    19.
    发明授权
    Data path for data extraction from streaming data 有权
    从数据流数据提取数据路径

    公开(公告)号：US08804764B2

    公开(公告)日：2014-08-12

    申请号：US12974689

    申请日：2010-12-21

    申请人： Francois Abel ,  Jean L. Cavignac ,  Christoph Hagleitner ,  Jonathan B. Rohrer ,  Jan Van Lunteren ,  Fabrice J. Verplanken

    发明人： Francois Abel ,  Jean L. Cavignac ,  Christoph Hagleitner ,  Jonathan B. Rohrer ,  Jan Van Lunteren ,  Fabrice J. Verplanken

    IPC分类号： H04J3/24

    CPC分类号： H04J3/1682

    摘要： A data path for streaming data includes a plurality of sequential data registers, each of the plurality of sequential data registers comprising a plurality of data fields, wherein the streaming data moves sequentially through the sequential data registers; and a multiplexing unit, the multiplexing unit configured such that the multiplexing unit has access to each of the plurality of data fields of the plurality of sequential data registers, and wherein the multiplexing unit is configured to extract data from the streaming data as the streaming data moves through the sequential data registers in response to a data request.

    摘要翻译： 用于流数据的数据路径包括多个顺序数据寄存器，所述多个顺序数据寄存器中的每一个包括多个数据字段，其中所述流数据顺序地通过所述顺序数据寄存器移动; 以及多路复用单元，所述复用单元被配置为使得所述复用单元能够访问所述多个顺序数据寄存器中的所述多个数据字段中的每一个，并且其中所述复用单元被配置为从所述流式数据中提取数据作为所述流数据 响应于数据请求，移动顺序数据寄存器。

    Hash collision reduction system
    20.
    发明授权
    Hash collision reduction system 有权
    哈希碰撞减少系统

    公开(公告)号：US08762399B2

    公开(公告)日：2014-06-24

    申请号：US13475990

    申请日：2012-05-20

    申请人： Jean L. Calvignac ,  Casimer M. DeCusatis ,  Fabrice J. Verplanken ,  Daniel Wind

    发明人： Jean L. Calvignac ,  Casimer M. DeCusatis ,  Fabrice J. Verplanken ,  Daniel Wind

    IPC分类号： G06F17/30

    CPC分类号： G06F17/30002 ,  G06F17/30949 ,  H04L9/00 ,  H04L9/3236 ,  H04L45/7453

    摘要： An improved computer system that can include a controller having a computer processor, the controller to reduce insertion times and/or collisions when interfacing with new components introduced to the controller. The system may also include a collision avoidance apparatus that reduces hashing collisions by using a plurality of tables and a plurality of keys per bucket. The system may further include a hash apparatus in communication with the controller to map the plurality of keys to the plurality of tables where the hash apparatus uses a single hash logic to provide an avalanche effect when one key is changed which results in nearly half of bits changing in the plurality of tables.

    摘要翻译： 一种改进的计算机系统，其可以包括具有计算机处理器的控制器，所述控制器在与引入到控制器的新组件接口时减少插入时间和/或冲突。 该系统还可以包括通过使用多个表和每个桶的多个密钥来减少散列冲突的冲突避免装置。 该系统还可以包括与控制器通信的散列装置，以将多个密钥映射到多个表，其中散列装置使用单个散列逻辑以在一个密钥改变时提供雪崩效应，这导致几乎一半的比特 改变多个表。