Method and apparatus for controlling a circuit with a high voltage sense device
    11.
    发明授权
    Method and apparatus for controlling a circuit with a high voltage sense device 有权
    用高压检测装置控制电路的方法和装置

    公开(公告)号:US08120097B2

    公开(公告)日:2012-02-21

    申请号:US12975224

    申请日:2010-12-21

    Inventor: Donald R. Disney

    Abstract: A control circuit with a high voltage sense device. In one embodiment, a circuit includes a first transistor disposed in a first substrate having first, second and third terminals. A first terminal of the first transistor is coupled to an external voltage. A voltage provided at a third terminal of the first transistor is substantially proportional to a voltage between the first and second terminals of the first transistor when the voltage between the first and second terminals of the first transistor is less than a pinch-off voltage of the first transistor. The voltage provided at the third terminal of the first transistor is substantially constant and less than the voltage between the first and second terminals of the first transistor when the voltage between the first and second terminals of the first transistor is greater than the pinch-off voltage of the first transistor. The circuit also includes a control circuit disposed in the first substrate and coupled to the third terminal of the first transistor. The circuit further includes a second transistor disposed in a second substrate. A first terminal of the second transistor coupled to the external voltage.

    Abstract translation: 具有高电压检测装置的控制电路。 在一个实施例中,电路包括设置在具有第一,第二和第三端子的第一基板中的第一晶体管。 第一晶体管的第一端子耦合到外部电压。 当第一晶体管的第一和第二端子之间的电压小于第一晶体管的钳位电压时,设置在第一晶体管的第三端处的电压基本上与第一晶体管的第一和第二端子之间的电压成比例, 第一晶体管。 当第一晶体管的第一端和第二端之间的电压大于夹断电压时,在第一晶体管的第三端处提供的电压基本上恒定且小于第一晶体管的第一和第二端之间的电压 的第一晶体管。 电路还包括设置在第一基板中并耦合到第一晶体管的第三端子的控制电路。 电路还包括设置在第二基板中的第二晶体管。 第二晶体管的第一端子耦合到外部电压。

    LOW LOSS DISCHARGE CIRCUITS FOR EMI FILTER CAPACITORS
    12.
    发明申请
    LOW LOSS DISCHARGE CIRCUITS FOR EMI FILTER CAPACITORS 有权
    用于EMI滤波电容器的低损耗放电电路

    公开(公告)号:US20120007567A1

    公开(公告)日:2012-01-12

    申请号:US12956351

    申请日:2010-11-30

    CPC classification number: H02M1/44 H02M1/32 H02M2001/322

    Abstract: A discharge circuit for an EMI filter capacitor includes normally-ON transistors. The normally-ON transistors may be controlled to limit current through them when an AC source is coupled across the discharge circuit. When the AC source is disconnected from the discharge circuit, the normally-ON transistors turn ON to allow current flow through them. The current flow allows the EMI filter capacitor to be discharged by a discharge resistor.

    Abstract translation: 用于EMI滤波电容器的放电电路包括常开晶体管。 当AC源耦合在放电电路两端时,可以控制常ON晶体管以限制通过它们的电流。 当交流电源与放电电路断开连接时,常开晶体管导通,允许电流流过它们。 电流流过允许EMI滤波电容通过放电电阻放电。

    Trench-gate MOSFET with capacitively depleted drift region
    14.
    发明授权
    Trench-gate MOSFET with capacitively depleted drift region 有权
    具有电容耗尽漂移区的沟槽栅极MOSFET

    公开(公告)号:US07977193B1

    公开(公告)日:2011-07-12

    申请号:US12908774

    申请日:2010-10-20

    CPC classification number: H01L29/7813 H01L29/407 H01L29/42376 H01L29/66734

    Abstract: A trench-gate metal oxide semiconductor field-effect transistor includes a field plate that extends into a drift region of the transistor. The field plate is configured to deplete the drift region when the transistor is in the OFF-state. The field plate is formed in a field plate trench. The field plate trench may be formed using a self-aligned etch process. The conductive material of the field plate and gate of the transistor may be deposited in the same deposition process step. The conductive material may be etched thereafter to form the field plate and the gate in the same etch process step.

    Abstract translation: 沟槽栅极金属氧化物半导体场效应晶体管包括延伸到晶体管的漂移区域的场板。 场板配置为在晶体管处于截止状态时耗尽漂移区域。 场板形成在场板沟槽中。 场板沟槽可以使用自对准蚀刻工艺形成。 晶体管的场板和栅极的导电材料可以在相同的沉积工艺步骤中沉积。 之后可以蚀刻导电材料,以在相同的蚀刻工艺步骤中形成场板和栅极。

    Processes for forming isolation structures for integrated circuit devices
    15.
    发明授权
    Processes for forming isolation structures for integrated circuit devices 有权
    用于形成用于集成电路器件的隔离结构的工艺

    公开(公告)号:US07939420B2

    公开(公告)日:2011-05-10

    申请号:US12070036

    申请日:2008-02-14

    Abstract: Processes for forming isolation structures for semiconductor devices include forming a submerged floor isolation region and a filed trench which together enclose an isolated pocket of the substrate. One process aligns the trench to the floor isolation region. In another process a second, narrower trench is formed in the isolated pocket and filled with a dielectric material while the dielectric material is deposited so as to line the walls and floor of the first trench. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.

    Abstract translation: 用于形成用于半导体器件的隔离结构的工艺包括形成浸没的底部隔离区域和一起封装衬底的隔离袋状物的沟槽。 一个过程将沟槽对准地板隔离区域。 在另一种方法中,在隔离的袋中形成第二较窄的沟槽,并且填充介电材料,同时沉积电介质材料以便使第一沟槽的壁和底板成线。 衬底不含有外延层,从而克服了与其制造相关的许多问题。

    POWER DEVICES AND ASSOCIATED METHODS OF MANUFACTURING
    16.
    发明申请
    POWER DEVICES AND ASSOCIATED METHODS OF MANUFACTURING 审中-公开
    电力设备及相关制造方法

    公开(公告)号:US20110068397A1

    公开(公告)日:2011-03-24

    申请号:US12566575

    申请日:2009-09-24

    Inventor: Donald R. Disney

    Abstract: Power devices and associated methods of manufacturing are disclosed herein. In one embodiment, a power device includes a drain at a first end, a source and a gate at a second end, and a drift region between the drain at the first end and the source at the second end. The drift region includes a p-type dopant column juxtaposed with an n-type dopant column. The p-type dopant column and the n-type dopant column together have a width less than 12 microns.

    Abstract translation: 功率器件和相关的制造方法在此公开。 在一个实施例中,功率器件包括在第一端处的漏极,源极和第二端的栅极,以及在第一端处的漏极和在第二端处的源极之间的漂移区域。 漂移区域包括与n型掺杂剂柱并列的p型掺杂剂柱。 p型掺杂剂柱和n型掺杂剂柱一起具有小于12微米的宽度。

    Isolated diode
    17.
    发明授权
    Isolated diode 有权
    隔离二极管

    公开(公告)号:US07834421B2

    公开(公告)日:2010-11-16

    申请号:US12072653

    申请日:2008-02-27

    Abstract: Various integrated circuit devices, in particular a diode, are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. Various techniques for terminating the isolation structure by extending the floor isolation region beyond the trench, using a guard ring, and a forming a drift region are described.

    Abstract translation: 各种集成电路装置,特别是二极管,形成在隔离结构内部,该隔离结构包括底板隔离区域和从衬底表面延伸到地板隔离区域的沟槽。 沟槽可以填充有介电材料,或者可以在中间部分具有导电材料,其中介电层衬在沟槽的壁上。 描述了通过使用保护环将基底隔离区域延伸超过沟槽并形成漂移区域来终止隔离结构的各种技术。

    Method and apparatus for controlling a circuit with a high voltage sense device
    18.
    发明授权
    Method and apparatus for controlling a circuit with a high voltage sense device 有权
    用高压检测装置控制电路的方法和装置

    公开(公告)号:US07696566B2

    公开(公告)日:2010-04-13

    申请号:US12350147

    申请日:2009-01-07

    Inventor: Donald R. Disney

    Abstract: A control circuit with a high voltage sense device. In one embodiment, a circuit includes a first transistor disposed in a first substrate having first, second and third terminals. A first terminal of the first transistor is coupled to an external voltage. A voltage provided at a third terminal of the first transistor is substantially proportional to a voltage between the first and second terminals of the first transistor when the voltage between the first and second terminals of the first transistor is less than a pinch-off voltage of the first transistor. The voltage provided at the third terminal of the first transistor is substantially constant and less than the voltage between the first and second terminals of the first transistor when the voltage between the first and second terminals of the first transistor is greater than the pinch-off voltage of the first transistor. The circuit also includes a control circuit disposed in the first substrate and coupled to the third terminal of the first transistor. The circuit further includes a second transistor disposed in a second substrate. A first terminal of the second transistor coupled to the external voltage.

    Abstract translation: 具有高电压检测装置的控制电路。 在一个实施例中,电路包括设置在具有第一,第二和第三端子的第一基板中的第一晶体管。 第一晶体管的第一端子耦合到外部电压。 当第一晶体管的第一和第二端子之间的电压小于第一晶体管的钳位电压时,设置在第一晶体管的第三端处的电压基本上与第一晶体管的第一和第二端子之间的电压成比例, 第一晶体管。 当第一晶体管的第一端和第二端之间的电压大于夹断电压时,在第一晶体管的第三端处提供的电压基本上恒定且小于第一晶体管的第一和第二端之间的电压 的第一晶体管。 电路还包括设置在第一基板中并耦合到第一晶体管的第三端子的控制电路。 电路还包括设置在第二基板中的第二晶体管。 第二晶体管的第一端子耦合到外部电压。

    Electronic circuit control element with tap element
    20.
    发明授权
    Electronic circuit control element with tap element 有权
    带抽头元件的电子电路控制元件

    公开(公告)号:US07333351B2

    公开(公告)日:2008-02-19

    申请号:US11495382

    申请日:2006-07-28

    Inventor: Donald R. Disney

    Abstract: A technique for controlling a power supply with power supply control element with a tap element. In one embodiment, a power supply regulator includes a power transistor having first, second, third and fourth terminals. A control circuit is included, which is coupled to the third and fourth terminals of the power transistor. The power transistor is configured to switch a current between the first and second terminals in response a control signal received from the control circuit at the third terminal. A voltage between the fourth and second terminals of the power transistor is substantially proportional to a current flowing between the first and second terminals when a voltage between the first and second terminals is less than a pinch off voltage. The voltage between the fourth and second terminals of the power transistor is substantially constant and less than the voltage between the first and second terminals when the voltage between the first and second terminals is greater than the pinch off voltage.

    Abstract translation: 一种用电源控制元件与抽头元件控制电源的技术。 在一个实施例中,电源调节器包括具有第一,第二,第三和第四端子的功率晶体管。 包括控制电路,其耦合到功率晶体管的第三和第四端子。 功率晶体管被配置为响应于从第三端子处的控制电路接收的控制信号在第一和第二端子之间切换电流。 当第一和第二端子之间的电压小于夹断电压时,功率晶体管的第四和第二端子之间的电压基本上与在第一和第二端子之间流动的电流成比例。 当第一和第二端子之间的电压大于夹断电压时,功率晶体管的第四和第二端子之间的电压基本上是恒定的,并且小于第一和第二端子之间的电压。

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