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公开(公告)号：US20190010601A1
公开(公告)日：2019-01-10
申请号：US15745338
申请日：2017-06-13
Inventor： Zhiming LIN , Zhen WANG
Abstract: A mask, a method for manufacturing a mask, and a mask assembly are disclosed. The mask includes an effective region for evaporation and an edge region between an edge of the effective region for evaporation extending in a stretching direction and an edge of the mask extending in the stretching direction. The edge region is provided with a bending relieving structure for relieving a curling of the edge of the effective region for evaporation when the mask is stretched in the stretching direction.
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公开(公告)号：US20190010599A1
公开(公告)日：2019-01-10
申请号：US15744958
申请日：2017-07-03
Inventor： Zhiming LIN , Zhen WANG , Jian ZHANG
Abstract: A mask and an assembling method are provided. The mask includes a plurality of strip-shaped supporting structures; a mask sheet supported by adjacent supporting structures, having a mask pattern; and a frame having an opening area; each of the supporting structures includes an intermediate portion and extension portions at both ends of the supporting structure, a width of the intermediate portion is greater than a width of each of the extension portions; the frame is provided with a groove connected with the opening area; and the extension portions of the supporting structure and an transition area in the intermediate portion close to the extension portion are located in the groove, and a fixing point configured to fix the supporting structure with the groove is at least disposed in the transition area.
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公开(公告)号：US20190003033A1
公开(公告)日：2019-01-03
申请号：US15576524
申请日：2017-05-10
Inventor： Shanshan BAI
Abstract: A mask plate and a method for manufacturing the same are provided. The mask plate comprises a first sub-mask plate and a second sub-mask plate stacked with each other, the first sub-mask plate is provided with at least one first opening therein, a size and a shape of the first opening correspond to those of a target display panel; the second sub-mask plate is provided with a second opening region, which covers at least one of the at least one first opening and includes a plurality of second openings. Since it is only required to ensure that the sizes and shapes of the first openings are the same as those of the target display panels respectively, and it is unnecessary to further manufacture openings for forming pixel patterns, comparing with the existing mask plate, the manufacturing process of the present disclosure is more simple and the manufacturing cost is lower.
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公开(公告)号：US10156505B2
公开(公告)日：2018-12-18
申请号：US14778881
申请日：2015-01-16
Inventor： Fengli Ji , Minghua Xuan , Shanshan Bai , Jiantao Liu , Jingbo Xu
Abstract: The present invention discloses an analysis method of a tensioning process of a fine mask plate. The analysis method, based on the simulation function of ANSYS software, finds an appropriate tensile force for stretching a fine mask plate and a corresponding actual counterforce applied to a metal frame before each fine mask plate is welded onto the metal frame through establishing a finite element model of the fine mask plate and a finite element model of the metal frame. The analysis process requires no physical tests, thereby effectively avoiding damaging the fine mask plate and further effectively saving the test cost.
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公开(公告)号：US20180342187A1
公开(公告)日：2018-11-29
申请号：US15759722
申请日：2017-09-13
Inventor： Yue SHAN , Jun FAN , Jiguo WANG , Yishan FU , Mingchao MA
CPC classification number: G09G3/20 , G09G2310/0286 , G09G2310/06 , G11C19/28 , G11C19/287
Abstract: A shift register, a gate driving circuit, a display panel and a driving method. The shift register includes: an input circuit, an output circuit, a pull-up-node pull-down circuit, a first control circuit, a second control circuit and an output pull-down circuit. The first control circuit is configured to write a fourth clock signal into a first pull-down node and write a first power voltage into a second pull-down node responsive to a first control signal, and to write the first power voltage into the first pull-down node responsive to a voltage of a pull-up node. The second control circuit is configured to write the fourth clock signal into the second pull-down node and write the first power voltage into the first pull-down node responsive to a second control signal, and to write the first power voltage into the second pull-down node responsive to the voltage of the pull-up node.
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Patent Agency Ranking
186.发明申请公开(公告)号：US20180335884A1
公开(公告)日：2018-11-22
申请号：US15768710
申请日：2017-07-18
Inventor： Jie Zhang
Abstract: The present invention is related to a gate driving circuit. The gate driving circuit may comprise at least two scan modules coupled to a same clock signal. Each of the at least two scan modules may have an input terminal, a reset terminal, and at least one stage of shift register unit. The reset terminal of at least one of the at least two scan modules is coupled to a touch control enable signal line.
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公开(公告)号：US20180315374A1
公开(公告)日：2018-11-01
申请号：US15569243
申请日：2017-04-17
Inventor： Yi ZHANG , Kai ZHANG , Minghua XUAN , Young Yik KO , Lujiang HUANGFU
IPC: G09G3/3258
Abstract: A pixel circuit, a display panel, a display device and a driving method. The pixel circuit includes a storage capacitor, an organic light emitting diode, a driving transistor, an emission control circuit, a reset circuit, a threshold compensation circuit, a first data write circuit, a reference voltage write circuit, and an initializing circuit.
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公开(公告)号：US20180308433A1
公开(公告)日：2018-10-25
申请号：US16023677
申请日：2018-06-29
Inventor： Chenggeng ZHANG , Boya ZHANG
IPC: G09G3/3283 , H02M1/32 , G09G3/3208 , H02M1/36 , H03K3/012 , H05B33/08
CPC classification number: G09G3/3283 , G09G3/3208 , G09G2300/0426 , G09G2310/08 , G09G2330/028 , G09G2330/04 , H02M1/32 , H02M1/36 , H03K3/012 , H05B33/0809 , H05B33/0896
Abstract: The present disclosure discloses an enable signal generation circuit, comprising: an input module configured to input a direct current signal from the first input terminal to a first node; a transmission module configured to transmit the direct current signal at the first node to an output terminal; a first conducting module and a second conducting module configured to conduct signals in an alternating current signal from the second input terminal to the first node; a first filter module configured to filter the signal at the first node such that, at the first node, the alternating current signal from the second input terminal is conducted to a common terminal. The second input terminal is connected to the output terminal. The present disclosure simplifies the circuit structure and solves the problem caused by the difference between timing sequences of inputted signals.
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公开(公告)号：US20180292934A1
公开(公告)日：2018-10-11
申请号：US15566572
申请日：2017-04-19
Inventor： Haifeng XU , Dawei SHI , Wentao WANG , Lu YANG , Jinfeng WANG , Xiaowen SI , Lei YAO , Lei YAN , Zifeng WANG , Liman PENG , Wenxiu LI , Lei WANG , Yaoda HOU , Xingyu PENG
IPC: G06F3/047
CPC classification number: G06F3/047 , G06F3/0412 , G06F3/0416 , G06F3/044 , G06F2203/04103
Abstract: A touch structure, an array substrate and a display device are provided. The touch structure includes touch electrodes and touch electrode lines including a first touch electrode line and a second touch electrode line connected with different touch electrodes. The first touch electrode line includes a first wire and a second wire which are mutually connected. The first wire is connected with the touch electrode, which is connected with the first touch electrode line, via a first through hole running through the insulation layer. The second wire is connected with the touch electrode, which is connected with the first touch electrode line, via a second through hole running through the insulation layer. At least a part of the second touch electrode line is between the second through hole and the first through hole in an arrangement direction of the touch electrode lines.
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公开(公告)号：US10090831B2
公开(公告)日：2018-10-02
申请号：US15122389
申请日：2015-04-09
Inventor： Jun Wang , Xinxin Jin , Liang Sun , Yuebai Han , Guoqing Zhang
IPC: G09G3/3233 , H03K17/16
Abstract: The present disclosure relates to a method of electrically aging a PMOS thin film transistor. The method includes applying a first voltage Vg with an amplitude of A volts to a gate of the PMOS thin film transistor; applying a second voltage Vs with an amplitude of (A−40) to (A−8) volts to a source of the PMOS thin film transistor; and applying a third voltage Vd with an amplitude of (A−80) to (A−16) volts to a drain of the PMOS thin film transistor. Application of the first voltage Vg, the second voltage Vs and the third voltage Vd is maintained for a predetermined time period, and Vd−Vs
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