-
公开(公告)号：US20190051243A1
公开(公告)日：2019-02-14
申请号：US15570928
申请日：2017-05-19
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Quanhu LI , Yongqian LI , Pan XU , Yu WANG , Song MENG , Fei YANG , Baoxia ZHANG , Cuili GAI , Ling WANG , Yicheng LIN , Kun CAO , Longyan WANG , Yue WU
IPC: G09G3/3258 , G09G3/3233 , G09G3/20 , G09G3/3275 , H01L27/32
Abstract: A pixel driving circuit, a pixel driving method, an array substrate, a display device, and a display panel are disclosed. The pixel driving circuit includes a switching subcircuit, a plurality of clock signal lines, a data writing subcircuit and a driving subcircuit.
-
公开(公告)号：US20180314283A1
公开(公告)日：2018-11-01
申请号：US15852330
申请日：2017-12-22
Inventor： Xuehuan FENG , Pan XU , Yongqian LI , Zhongyuan WU
CPC classification number: G05F1/575 , G05F1/561 , G05F1/563 , H03K5/1534 , H03K5/2481 , H03K21/026
Abstract: The present invention provides a digital low dropout regulator and a control method thereof. The regulator comprises a voltage comparator, a counter, a decoder, a PMOSFET array and a divider. The voltage comparator receives an actual voltage output from the PMOSFET array through the positive input terminal, receives a reference voltage through the negative input terminal, and compares the actual voltage and the reference voltage to obtain a level signal. The divider calculates based on an output voltage pre-configured for a PMOSFET array and an actual voltage output by the PMOSFET array in at least two clock cycles to obtain a first value. The counter generates a control signal based on the level signal and the first value. The decoder receives the control signal transmitted by the counter and controlling the number of switched-on transistors, in the PMOSFET on a basis of the control signal.
-
公开(公告)号：US20180005556A1
公开(公告)日：2018-01-04
申请号：US15540752
申请日：2016-11-09
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Pan XU , Guangcai YUAN , Yongqian LI , Dongxu HAN
IPC: G09G3/00 , G09G3/3225
CPC classification number: G09G3/006 , G09G3/00 , G09G3/3225 , G09G2310/08 , G09G2330/02 , G09G2330/10
Abstract: A test method of a display panel and a test device are disclosed. The test method includes outputting a data signal of a preset test image to the display panel to cause plural light emitting elements to emit light according to the preset test image; outputting a starting signal to a scan circuit in the display panel to cause the scan circuit to output an active level of a switching circuit to the plural rows of first scan lines as connected, successively, according to a preset timing sequence; receiving a sensing signal from a sensor circuit, including voltage value information of a first terminal of every light emitting element; comparing the voltage value information of the first terminal of every light emitting element with the preset test image to obtain a test result. The test method solves the problem of missing detection of Mura.
-
公开(公告)号：US20170140707A1
公开(公告)日：2017-05-18
申请号：US15322471
申请日：2016-03-21
Inventor： Pan XU , Zhongyuan WU , Yuting ZHANG , Yongqian LI
IPC: G09G3/3258
CPC classification number: G09G3/3258 , G09G3/3233 , G09G2300/0426 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2310/0289 , G09G2320/0233 , G09G2320/045 , G09G2330/028
Abstract: A pixel driving circuit, a pixel driving method and a display apparatus are provided. The pixel driving circuit includes a reset unit, a threshold compensation unit, a data writing unit, a drive transistor, a first storage capacitor and a light emitting device. According to the present disclosure, it is able to make the drive current generated by the drive transistor only related to the data voltage and the reference voltage but uncorrelated to the threshold voltage of the drive transistor when the drive transistor drives the light emitting device to display.
-
公开(公告)号：US20250124877A1
公开(公告)日：2025-04-17
申请号：US18578059
申请日：2023-04-28
Applicant: Hefei BOE Joint Technology Co., Ltd. , BOE TECHNOLOGY GROUP CO., LTD. , Beijing BOE Technology Development Co., Ltd.
Inventor： Xuehuan FENG , Yongqian LI , Xing YAO
IPC: G09G3/3266 , G11C19/28
Abstract: A shift register is provided and includes a display input reset circuit, an inverter circuit, at least one output circuit and a first detection circuit; the display input reset circuit, the inverter circuit and the output circuit are connected to a pull-up node; the inverter circuit and the at least one output circuit are connected to a pull-down node; the first detection circuit is connected to a signal acquisition point, an acquisition control terminal, and a first signal detection line, and configured to acquire a voltage at the signal acquisition point in response to a signal from the acquisition control terminal and output a detection voltage corresponding to the acquired voltage to the first signal detection line, an external first chip adjusts an active level voltage from the third power supply terminal according to the detection voltage; the signal acquisition point includes the pull-down node and/or a signal output terminal.
-
Patent Agency Ranking
公开(公告)号：US20250098448A1
公开(公告)日：2025-03-20
申请号：US18558269
申请日：2022-04-29
Inventor： Can YUAN , Yongqian LI , Dacheng ZHANG
IPC: H10K59/131 , G09G3/3233 , H10K59/124
Abstract: A display substrate, a method for operating the same, and a display device are provided. The display substrate includes a base substrate and a display unit. In the sub-pixel of the display substrate, the light emitting device includes a first electrode including a first portion and a second portion spaced apart from each other; the display unit further includes a connection structure and a first transfer electrode, the connection structure is electrically connected with the first portion of the first electrode and the second portion of the first electrode, and includes a connection portion located in the non-light-emitting region; the first transfer electrode is electrically connected with the first pole of the driving transistor and includes a portion located in the non-light-emitting region, and the connection portion is electrically connected with the portion of the first transfer electrode located in the non-light-emitting region.
-
公开(公告)号：US20250095571A1
公开(公告)日：2025-03-20
申请号：US18555023
申请日：2023-01-12
Inventor： Zhidong YUAN , Can YUAN , Dacheng ZHANG , Yongqian LI
IPC: G09G3/3233
Abstract: A display substrate and a display device are disclosed, the display substrate has a plurality of display partitions arranged in a plurality of rows and columns, and at least one display partition includes a plurality of sub-pixels; the display substrate includes a base substrate and common scanning signal lines, the common scanning signal lines are provided on the base substrate, and include a plurality of first common scanning signal lines extending along a first direction and a plurality of second common scanning signal lines extending along a second direction, and the first direction is different from the second direction; each of the plurality of second common scanning signal lines is electrically connected to one first common scanning signal line, and is configured to provide a common scanning signal to one display partition.
-
公开(公告)号：US20250029562A1
公开(公告)日：2025-01-23
申请号：US18279905
申请日：2022-10-27
Inventor： Xuehuan FENG , Yongqian LI
IPC: G09G3/3266 , G09G3/00 , G09G3/3233 , G11C19/28
Abstract: The present disclosure provides a shift register unit, including: a first sensing control input circuit and at least one first output circuit; the shift register unit further includes: a first voltage control circuit, a first sensing input leakage prevention circuit and a first current limiting circuit; the first sensing control input circuit is connected to a first pull-up node through the first sensing input leakage prevention circuit, the first sensing control input circuit is connected to the first sensing input leakage prevention circuit at a first sensing input leakage prevention node connected to a first voltage control node, the first sensing input leakage prevention circuit is connected to the clock control signal input terminal and is configured to control on/off between the first sensing input leakage prevention node and the first pull-up node; the first current limiting circuit is connected to the first voltage control node.
-
公开(公告)号：US20240404476A1
公开(公告)日：2024-12-05
申请号：US18261113
申请日：2022-05-24
Inventor： Zhidong YUAN , Yongqian LI , Can YUAN
IPC: G09G3/3266 , G09G3/3225
Abstract: A display substrate includes N groups of gate driving circuits and a multiplex circuit. Each group of gate driving circuits includes X gate driving circuits, and each gate driving circuit is electrically connected to rows of pixel circuits in a corresponding display zone. The X gate driving circuits are configured to output X scan signals of different functions to the rows of pixel circuits connected thereto. The multiplex circuit is electrically connected to N gate driving circuits of the N groups of gate driving circuits outputting scan signals of the same function, N selection control signal terminals and a start signal terminal. The multiplex circuit is configured to, under at least one selection control signal from at least one selection control signal terminal, select at least one group of gate driving circuits, and transmit a start signal from the start signal terminal to each selected group of gate driving circuits.
-
公开(公告)号：US20240373687A1
公开(公告)日：2024-11-07
申请号：US18249359
申请日：2022-03-07
Inventor： Liu WU , Zhidong YUAN , Yongqian LI , Can YUAN
IPC: H10K59/131 , H10K59/10 , H10K59/121
Abstract: A profiled display panel, including a display area. The display area includes a plurality of display sub-areas; a plurality of cascade signal lines for coupling adjacent two of the gate driving sub-circuits. At least one cascade signal line includes a first cascade trace extending in a first direction and a second cascade trace extending in a second direction. The first cascade trace includes a plurality of first conductive patterns arranged on a first conductive layer and second conductive pattern arranged on a second conductive layer. The plurality of first conductive patterns are electrically connected to the second conductive pattern; and the second cascade trace includes a third conductive pattern arranged on the first conductive layer.
-
-
-
-
-
-
-
-
-
Search Results
264
records
(took 0.022 seconds)
