公开(公告)号：US12205540B2

公开(公告)日：2025-01-21

申请号：US17764395

申请日：2021-03-18

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jiangnan Lu ,  Guangliang Shang ,  Xinshe Yin ,  Libin Liu ,  Jianchao Zhu ,  Hao Zhang ,  Ke Feng

IPC: G09G3/3233 ,  G09G3/3258 ,  G09G3/3266 ,  G09G3/36 ,  G11C19/28

Abstract: A shift register unit, a driving method thereof, a gate driving circuit and a display panel are provided. The shift register unit includes an input circuit, a reset circuit, a first output circuit and a second output circuit; the input circuit is configured to control a level of a first node in response to a first input signal; the reset circuit is configured to reset the first node in response to a reset signal; the first output circuit is configured to output a shift signal under control of the level of the first node; and the second output circuit is configured to, in a first phase, under control of the level of the first node, output a plurality of sub-pulses at the first output terminal as a first output signal in a case where the shift output terminal outputs a first level of the shift signal.

公开(公告)号：US12108643B2

公开(公告)日：2024-10-01

申请号：US17953941

申请日：2022-09-27

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jiangnan Lu ,  Guangliang Shang ,  Can Zheng ,  Yu Feng ,  Libin Liu ,  Jie Zhang ,  Mei Li

IPC: H10K59/131 ,  G09G3/3208 ,  H10K59/121

CPC classification number: H10K59/131 ,  H10K59/121 ,  G09G3/3208 ,  G09G2320/0209 ,  G09G2320/0233

Abstract: Provided is a display substrate, the display substrate is provided with a display area and a peripheral area around the display area, and includes: a source/drain layer, a planarization layer and an anode layer which are laminated in sequence, wherein in the peripheral area, the source/drain layer includes at least one pair of first signal lines including a signal line of a gate circuit and the anode layer includes a common power line provided with vent holes; and overlapping areas between two first signal lines in any pair of the first signal lines and a projection pattern of the vent hole are equal, the projection pattern of the vent hole being a pattern of an orthographic projection of the vent hole in the common power line onto the source/drain layer. A display panel and a display device are also provided.

公开(公告)号：US11875748B2

公开(公告)日：2024-01-16

申请号：US17433668

申请日：2021-02-24

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang Shang ,  Tian Dong ,  Xinshe Yin ,  Mei Li ,  Libin Liu ,  Shiming Shi

IPC: G11C19/28 ,  G09G3/3266 ,  G09G3/3233 ,  G09G3/20

CPC classification number: G09G3/3266 ,  G11C19/28 ,  G09G3/20 ,  G09G3/3233 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2320/0247 ,  G09G2330/021

Abstract: Provided are a gate driving circuit, a display substrate, a display device and a gate driving method, the gate driving circuit includes: a frequency doubling control circuit and an effective output circuit including first shift registers, the first shift register at the first stage has a first signal input terminal coupled with an output control signal line and a second signal input terminal coupled with the frequency doubling control circuit; the frequency doubling control circuit is coupled to the output control signal line, for providing a frequency doubling control signal thereto after a preset time period from the receipt of the output control signal in response to an output control signal from the output control signal line; the first shift register at the first stage outputs a scanning signal in response to the output control signal and a scanning signal in response to the frequency doubling control signal.

公开(公告)号：US11862098B2

公开(公告)日：2024-01-02

申请号：US17628779

申请日：2021-04-09

Applicant: BOE Technology Group Co., Ltd.

Inventor： Guangliang Shang ,  Jie Zhang ,  Shuo Huang ,  Libin Liu ,  Shiming Shi ,  Hao Liu ,  Haoliang Zheng ,  Xing Yao

IPC: G09G3/3266 ,  G09G3/36 ,  G11C19/28

CPC classification number: G09G3/3266 ,  G09G3/3677 ,  G11C19/28 ,  G09G2300/0852 ,  G09G2310/0286

Abstract: A shift register, a driving method, a driving control circuit and a display device. The method comprises: at a data refresh stage (T10), applying to an input signal end (IP) an input signal having a pulse level, applying a control clock pulse signal to a control clock signal end, and applying a noise reduction clock pulse signal to a noise reduction clock signal end; at a noise reduction holding phase (T21-1), applying a fixed voltage signal to the input signal end (IP), applying a fixed voltage signal to the control clock signal end, and applying a fixed voltage signal to the noise reduction clock signal end; and at a noise reduction enhancement stage (T22-1), applying a fixed voltage signal to the input signal end (IP), applying a fixed voltage signal to the control clock signal end, and applying a clock pulse signal to the noise reduction clock signal end.

公开(公告)号：US11854508B2

公开(公告)日：2023-12-26

申请号：US17921082

申请日：2021-05-12

Applicant: BOE Technology Group Co., Ltd.

Inventor： Guangliang Shang ,  Tian Dong ,  Shuo Huang ,  Can Zheng

IPC: G09G3/36

CPC classification number: G09G3/3674 ,  G09G2310/0286

Abstract: A driving method and device for a shift register. In a data refreshing phase, loading an input signal having a pulse level to an input signal end, loading a control clock pulse signal to a control clock signal end, loading a noise reduction clock pulse signal to a noise reduction clock signal end, controlling a cascade signal end of the shift register to output a cascade signal having a pulse level, and controlling a drive signal end of the shift register to output a drive signal having a pulse level; in a data holding phase, loading a fixed voltage signal to the input signal end, loading a first set signal to the control clock signal end, loading a second set signal to the noise reduction clock signal end, controlling the cascade signal end to output a fixed voltage signal having a second level.

公开(公告)号：US11798458B2

公开(公告)日：2023-10-24

申请号：US17905620

申请日：2021-08-12

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang Shang ,  Jie Zhang ,  Jiangnan Lu ,  Mei Li ,  Libin Liu

IPC: G09G3/3266 ,  G09G3/20

CPC classification number: G09G3/2092 ,  G09G2300/0426 ,  G09G2300/0842 ,  G09G2310/0267 ,  G09G2330/021

Abstract: A gate driving unit includes a first input node control circuit and a charge pump circuit; the first input node control circuit is configured to connect or disconnect the between an input terminal and the first input node under control of a clock signal provided by the clock signal terminal; the charge pump circuit is configured to control to convert a voltage signal of the first input node into a voltage signal of the first node under the control of an input clock signal provided by the input clock signal terminal when the voltage signal of the first input node is a first voltage signal, so that a polarity of the voltage signal of the first input is the same as a polarity of the voltage signal of the first input node, and an absolute value of the voltage value of the voltage signal of the first node is greater than an absolute value of a voltage value of the voltage signal of the first input node.

公开(公告)号：US20230282170A1

公开(公告)日：2023-09-07

申请号：US18019987

申请日：2022-02-24

Applicant: BOE Technology Group Co., Ltd.

Inventor： Guangliang Shang ,  Libin Liu ,  Li Wang ,  Yu Feng ,  Baoyun Wu

IPC: G09G3/3266 ,  G11C19/28 ,  H10K59/121

CPC classification number: G09G3/3266 ,  G11C19/28 ,  H10K59/1213 ,  H10K59/1216 ,  G09G2300/0408 ,  G09G2310/0286 ,  G09G2310/0281 ,  G09G2300/0426

Abstract: A display substrate and a display device. The display substrate includes: a base substrate; and a gate driving circuit; the gate driving circuit includes a plurality of shift register circuits; each shift register circuit includes: an input circuit, a control circuit, an output circuit, and an output noise reduction circuit; the control circuit includes a first transistor, a second transistor, and a third transistor; the control circuit is connected to the first node, a second node and a third node; at least two selected from group consisting of an active layer of the first transistor, an active layer of the second transistor, and an active layer of the third transistor extend in a first direction and are arranged in the first direction.

公开(公告)号：US11670391B2

公开(公告)日：2023-06-06

申请号：US17435006

申请日：2020-09-28

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Li Wang ,  Guangliang Shang

IPC: G11C19/28 ,  G09G3/3266

CPC classification number: G11C19/28 ,  G09G3/3266 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/0286 ,  G09G2310/08

Abstract: A shift register includes: an input circuit transmitting a first signal to a first node in response to a first clock signal and a second signal, transmitting the second signal to the first node in response to the first clock signal and the first signal; a first control circuit transmitting the first clock signal to a second node in response to the first node, transmitting a first voltage to the second node in response to the first clock signal; a second control circuit transmitting a second voltage to a third node in response to the first node, transmitting a second clock signal to the third node in response to the second node and the second clock signal; an output circuit transmitting the first voltage to a signal output terminal in response to the first node, transmitting the second voltage to the signal output terminal in response to the third node.

公开(公告)号：US11335243B2

公开(公告)日：2022-05-17

申请号：US16904585

申请日：2020-06-18

Applicant: BOE Technology Group Co., Ltd.

Inventor： Haoliang Zheng ,  Minghua Xuan ,  Dongni Liu ,  Ning Cong ,  Zhenyu Zhang ,  Lijun Yuan ,  Yi Ouyang ,  Guangliang Shang

IPC: G09G3/32

Abstract: Disclosed are a display panel and a display device. The display panel includes M rows and N columns of pixel units. The display panel is divided into R regions along a column direction, and an i-th region includes: (1+M(i−1)/R)-th row to a (Mi/R)-th row of pixel units. The display panel further includes M shift registers, M light emitting drivers, R light emitting control scan staring signal terminals, R scan start signal terminals for controlling time length and R scan start signal terminals for controlling current. An i-th row of pixel units is connected with an i-th shift register and an i-th light emitting driver, a light emitting driver connected to a first row of pixel units in the i-th region is connected with an i-th scan start signal terminal for controlling light emission.

公开(公告)号：US11176886B2

公开(公告)日：2021-11-16

申请号：US16319185

申请日：2018-05-14

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Lijun Yuan ,  Mingfu Han ,  Zhichong Wang ,  Haoliang Zheng ,  Seungwoo Han ,  Guangliang Shang

IPC: G09G3/3258 ,  G09G3/3266 ,  G09G3/3275 ,  G09G3/3233 ,  G09G3/3208 ,  G09G3/3225

Abstract: The present disclosure discloses a circuit, a driving method thereof, a display panel and a display device. The circuit may include: a signal control module, a compensation control module, an initialization module, a data writing module, a driving control module, and a light emitting device. With the signal control module which is cooperated with other modules, the threshold voltage compensation time of the driving transistor can be increased, and the threshold voltage compensation can be ensured, thereby improving the image display quality.