公开(公告)号：US20230118565A1

公开(公告)日：2023-04-20

申请号：US18066464

申请日：2022-12-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Kang Fu ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/768

摘要： The present disclosure provides a method that includes depositing a metal layer onto a substrate, subtractive patterning the metal layer into first metal lines, and forming at least one second metal line between two adjacent ones of the first metal lines using a damascene process. The first metal lines have a different metallization structure from the at least one second metal line.

公开(公告)号：US11450602B2

公开(公告)日：2022-09-20

申请号：US16837762

申请日：2020-04-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Kang Fu ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/768

摘要： The present disclosure provides a method for forming semiconductor structures. The method includes providing a device having a substrate, a first dielectric layer over the substrate, and a first conductive feature over the first dielectric layer, the first conductive feature comprising a first metal, the first metal being a noble metal. The method also includes depositing a second dielectric layer over the first dielectric layer and covering at least sidewalls of the first conductive feature; etching the second dielectric layer to form a trench; and forming a second conductive feature in the trench. The second conductive feature comprises a second metal different from the first metal.

公开(公告)号：US20220157711A1

公开(公告)日：2022-05-19

申请号：US17097505

申请日：2020-11-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shao-Kuan Lee ,  Hsin-Yen Huang ,  Cheng-Chin Lee ,  Kuang-Wei Yang ,  Ting-Ya Lo ,  Chi-Lin Teng ,  Hsiao-Kang Chang ,  Shau-Lin Shue

IPC分类号： H01L23/522 ,  H01L21/768

摘要： The present disclosure relates an integrated chip. The integrated chip may include a first interconnect and a second interconnect disposed within a first inter-level dielectric (ILD) layer over a substrate. A lower etch stop structure is disposed on the first ILD layer and a third interconnect is disposed within a second ILD layer that is over the first ILD layer. The third interconnect extends through the lower etch stop structure to contact the first interconnect. An interconnect patterning layer is disposed on the second interconnect and laterally adjacent to the lower etch stop structure.

公开(公告)号：US20220157690A1

公开(公告)日：2022-05-19

申请号：US17097441

申请日：2020-11-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shao-Kuan Lee ,  Cherng-Shiaw Tsai ,  Ting-Ya Lo ,  Cheng-Chin Lee ,  Chi-Lin Teng ,  Kai-Fang Cheng ,  Hsin-Yen Huang ,  Hsiao-Kang Chang ,  Shau-Lin Shue

IPC分类号： H01L23/373 ,  H01L23/48 ,  H01L21/768

摘要： In some embodiments, the present disclosure relates to an integrated chip that includes an electrical interconnect structure, a thermal interconnect structure, and a thermal passivation layer over a substrate. The electrical interconnect structure includes interconnect vias and interconnect wires embedded within interconnect dielectric layers. The thermal interconnect structure is arranged beside the electrical interconnect structure and includes thermal vias, thermal wires, and/or thermal layers. Further, the thermal interconnect structure is embedded within the interconnect dielectric layers. The thermal passivation layer is arranged over a topmost one of the interconnect dielectric layers. The thermal interconnect structure has a higher thermal conductivity than the interconnect dielectric layers.

公开(公告)号：US20220068701A1

公开(公告)日：2022-03-03

申请号：US17501523

申请日：2021-10-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Kang Fu ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H01L21/321

摘要： A method of forming a semiconductor structure includes removing a top portion of a conductive feature disposed in a first dielectric layer and over a semiconductor substrate to form a first recess, depositing a second dielectric layer over the first dielectric layer, where the second dielectric layer includes a first region disposed vertically above the first recess and a second region disposed adjacent the first region, and forming a third dielectric layer over the second dielectric layer. The method further includes subsequently forming openings in the third dielectric layer that extend to expose the second dielectric layer, depositing a conductive material in the openings, and planarizing the conductive material to form conductive features in the first and the second regions, where the planarizing completely removes portions of the third dielectric layer disposed in the second region.

公开(公告)号：US20210398898A1

公开(公告)日：2021-12-23

申请号：US16908942

申请日：2020-06-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shin-Yi Yang ,  Hsin-Yen Huang ,  Ming-Han Lee ,  Shau-Lin Shue ,  Yu-Chen Chan ,  Meng-Pei Lu

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L21/768

摘要： In some embodiments, the present disclosure relates to an integrated chip that includes a lower dielectric arranged over a substrate. An interconnect wire is arranged over the dielectric layer, and a first interconnect dielectric layer is arranged outer sidewalls of the interconnect wire. A protection liner that includes graphene is arranged directly on the outer sidewalls of the interconnect wire and on a top surface of the interconnect wire. The integrated chip further includes a first etch stop layer arranged directly on upper surfaces of the first interconnect dielectric layer, and a second interconnect dielectric layer arranged over the first interconnect dielectric layer and the interconnect wire. Further, an interconnect via extends through the second interconnect dielectric layer, is arranged directly over the protection liner, and is electrically coupled to the interconnect wire.

公开(公告)号：US11205618B2

公开(公告)日：2021-12-21

申请号：US16571279

申请日：2019-09-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shin-Yi Yang ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L21/324

摘要： Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a third dielectric layer over the second dielectric layer, a second contact feature extending through the second dielectric layer and the third dielectric layer, and a graphene layer between the second contact feature and the third dielectric layer.

公开(公告)号：US20210375756A1

公开(公告)日：2021-12-02

申请号：US17402942

申请日：2021-08-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L23/522 ,  H01L21/027 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/321 ,  H01L23/532 ,  H01L23/528 ,  H01L21/311

摘要： A method of fabricating a semiconductor interconnect structure includes forming a via in a dielectric layer, depositing a ruthenium-containing conductive layer over a top surface of the via and a top surface of the dielectric layer, and patterning the ruthenium-containing conductive layer to form a conductive line over the top surface of the via, where a thickness of the conductive line is less than a thickness of the via.

公开(公告)号：US20210358803A1

公开(公告)日：2021-11-18

申请号：US16876465

申请日：2020-05-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shao-Kuan Lee ,  Hai-Ching Chen ,  Hsin-Yen Huang ,  Shau-Lin Shue ,  Cheng-Chin Lee

IPC分类号： H01L21/768 ,  H01L23/535 ,  H01L23/532

摘要： In some embodiments, the present disclosure relates to an integrated chip. The integrated chip may comprise a first metal line disposed over a substrate. A via may be disposed directly over a top of the first metal line and the via may comprise a first lower surface and a second lower surface above the first lower surface. A first dielectric structure may be disposed laterally adjacent to the first metal line and may be disposed along a sidewall of the first metal line. A first protective etch-stop structure may be disposed directly over a top of the first dielectric structure and the first protective etch-stop structure may vertically separate the second lower surface of the via from the top of the first dielectric structure.

公开(公告)号：US11094626B2

公开(公告)日：2021-08-17

申请号：US16534411

申请日：2019-08-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L23/522 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/321 ,  H01L21/027 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528

摘要： A method of fabricating a semiconductor interconnect structure includes forming a via in a dielectric layer, depositing a ruthenium-containing conductive layer over a top surface of the via and a top surface of the dielectric layer, and patterning the ruthenium-containing conductive layer to form a conductive line over the top surface of the via, where a thickness of the conductive line is less than a thickness of the via.