公开(公告)号：US11876051B2

公开(公告)日：2024-01-16

申请号：US17573781

申请日：2022-01-12

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Che-Hsien Liao ,  Yueh Hsu

IPC分类号： H01L23/532 ,  H01L23/528 ,  H01L21/768

CPC分类号： H01L23/53266 ,  H01L21/76846 ,  H01L21/76871 ,  H01L21/76889 ,  H01L23/5283

摘要： The present application discloses a conductive layer stack, a semiconductor device and methods for fabricating the conductive layer stack and the semiconductor device. The conductive layer stack includes an intervening layer comprising tungsten silicide and positioned on an under-layer; a filler layer comprising tungsten and positioned on the intervening layer. The under-layer comprises titanium nitride and comprises a columnar grain structure. A thickness of the intervening layer is greater than about 4.1 nm.

公开(公告)号：US11876045B2

公开(公告)日：2024-01-16

申请号：US18124748

申请日：2023-03-22

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chin-Ling Huang

IPC分类号： H01L23/525 ,  H01L23/532

CPC分类号： H01L23/5256 ,  H01L23/53238

摘要： The present disclosure provides a method for preparing a semiconductor device with a copper-manganese liner. The method includes forming an opening structure in a first dielectric layer, wherein the opening structure has a first portion, a second portion and a third portion disposed between and physically connecting the first portion and the second portion; forming a lining material lining the first portion and the second portion of the opening structure and completely filling the third portion of the opening structure, wherein the lining material includes copper-manganese (CuMn); filling the first portion and the second portion of the opening structure with a conductive material after the lining material is formed; and performing a planarization process on the lining material and the conductive material.

公开(公告)号：US20240015956A1

公开(公告)日：2024-01-11

申请号：US18470446

申请日：2023-09-20

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chung-Lin HUANG

IPC分类号： H10B12/00

CPC分类号： H10B12/488 ,  H10B12/34 ,  H10B12/053

摘要： A semiconductor device includes a substrate, a passing word line in the substrate, and a dielectric structure surrounding the passing word line. The dielectric structure has an enlargement portion at a bottom of the dielectric structure, and a maximum width of the enlargement portion of the dielectric structure is wider than a width of a top of the dielectric structure.

公开(公告)号：US20240014110A1

公开(公告)日：2024-01-11

申请号：US18195504

申请日：2023-05-10

申请人： NANYA TECHNOLOGY CORPORATION

发明人： CHIN-LING HUANG

IPC分类号： H01L23/498

CPC分类号： H01L23/49805 ,  H01L23/49822 ,  H01L23/49838

摘要： A semiconductor device is provided. The semiconductor device includes a body and an interconnection structure. The body has a first lateral surface and a second lateral surface angled relative to the first lateral surface. The interconnection structure is configured to make electrical connection between the semiconductor device and a first electronic component mounted to the first lateral surface of the body of the semiconductor device and to make electrical connection between the semiconductor device and a second electronic component mounted to the second lateral surface of the body of the semiconductor device.

公开(公告)号：US20240008252A1

公开(公告)日：2024-01-04

申请号：US17852416

申请日：2022-06-29

申请人： NANYA TECHNOLOGY CORPORATION

发明人： LU-WEI CHUNG

IPC分类号： H01L27/108

CPC分类号： H01L27/10808

摘要： The present disclosure provides a semiconductor structure having an air gap with a height greater than or equal to that of an adjacent bit line. The semiconductor structure includes a substrate; a first bit line structure disposed over the substrate; a second bit line structure disposed adjacent to the first bit line structure over the substrate; a first dielectric layer, surrounding the first bit line structure and the second bit line structure; and an air gap, disposed between the first bit line structure and the second bit line structure, and sealed by the first dielectric layer, wherein a height of the air gap is greater than or equal to a height of the first bit line structure.

公开(公告)号：US20240008250A1

公开(公告)日：2024-01-04

申请号：US17855949

申请日：2022-07-01

申请人： NANYA TECHNOLOGY CORPORATION

发明人： HSIH-YANG CHIU

IPC分类号： H01L27/108 ,  H01L49/02

CPC分类号： H01L27/10805 ,  H01L28/82

摘要： The present application provides a memory device having laterally extending capacitors of different lengths and levels. The memory device includes a semiconductor substrate; a first insulating layer disposed over the semiconductor substrate; a first bottom electrode disposed over the first insulating layer; a first dielectric layer disposed over the first bottom electrode; a first recess extending through the first dielectric layer; a first capacitor dielectric conformal to the first recess and in contact with the first bottom electrode; and a first top electrode disposed within the first recess and surrounded by the first capacitor dielectric, wherein the first capacitor dielectric and the first top electrode extend laterally over the first bottom electrode and the semiconductor substrate.

公开(公告)号：US20240004302A1

公开(公告)日：2024-01-04

申请号：US17810349

申请日：2022-07-01

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Yu-Chen HUANG

IPC分类号： G03F7/38 ,  H01L21/027 ,  G03F7/039

CPC分类号： G03F7/38 ,  G03F7/039 ,  H01L21/0274

摘要： A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate. A portion of the photoresist layer is exposed, using a mask, to a radiation. The photoresist layer is treated, using a basic gas. The photoresist layer is developed to form a patterned photoresist layer over the substrate.

公开(公告)号：US20230420307A1

公开(公告)日：2023-12-28

申请号：US17808917

申请日：2022-06-24

申请人： NANYA TECHNOLOGY CORPORATION

发明人： TZU-CHING TSAI

IPC分类号： H01L21/66 ,  C23C16/52

CPC分类号： H01L22/12 ,  C23C16/52

摘要： A deposition method includes executing a first deposition recipe on a first wafer to turn a first wafer state of the first wafer to a second wafer state; collecting the second wafer state of the first wafer to generate a first set of data; and analyzing the first set of data and update the first deposition recipe to a second deposition recipe when the first set of data is not within a predetermined range. The second deposition recipe is generated taking into consideration at least one of a deposition rate of the second wafer, a rate of rotation of the second wafer, a tilt angle of the second wafer, an etching recipe of the first wafer, and an implanting recipe of the first wafer. The second deposition recipe is configured to be applied on a second wafer to be processed after the first wafer.

公开(公告)号：US20230420306A1

公开(公告)日：2023-12-28

申请号：US17808912

申请日：2022-06-24

申请人： NANYA TECHNOLOGY CORPORATION

发明人： TZU-CHING TSAI

IPC分类号： H01L21/66 ,  H01L21/265

CPC分类号： H01L22/12 ,  H01L21/265

摘要： An implanting method includes executing a first implanting recipe on a first wafer to turn a first wafer state of the first wafer to a second wafer state; collecting the second wafer state of the first wafer to generate a first set of data; and analyzing the first set of data and update the first implanting recipe to a second implanting recipe when the first set of data is not within a predetermined range. The second implanting recipe is generated taking into consideration at least one of an implanting rate of the second wafer, a rate of rotation of the second wafer, a tilt angle of the second wafer, an etching recipe of the first wafer, and a deposition recipe of the first wafer. The second implanting recipe is configured to be applied on a second wafer to be processed after the first wafer.

公开(公告)号：US11854832B2

公开(公告)日：2023-12-26

申请号：US17665722

申请日：2022-02-07

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Shih-En Lin ,  Jui-Lin Chin

IPC分类号： H01L21/48

CPC分类号： H01L21/4846 ,  H01L21/481

摘要： A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a first metallization line, a second metallization line, a first isolation feature, a second isolation feature, a profile modifier, and a contact feature. The first metallization line and the second metallization line extend along a first direction. The first isolation feature and the second isolation feature are disposed between the first metallization line and the second metallization line. The first metallization line, the second metallization line, the first isolation feature and the second isolation feature define an aperture. The profile modifier is disposed within the aperture to modify a profile of the aperture in a plan view. The contact feature is disposed within the aperture.