公开(公告)号：US06633995B1

公开(公告)日：2003-10-14

申请号：US09522310

申请日：2000-03-09

Applicant: Kyung Woo Nam

Inventor： Kyung Woo Nam

IPC: G06F104

CPC classification number: G11C7/222 ,  G06F9/3869 ,  G11C7/1039

Abstract: A high-speed pipeline device includes n data path circuits connected in cascade between an input terminal and an output terminal. N data passing circuits have transmission times {T1, . . . , Tn} each less than a period P of a reference clock signal, at least one of the transmission times differing from another. N pipe registers connect to the input terminals of the data path circuits to latch data passed from a previous stage or the input terminal. A control signal generating circuit produces n pipeline control signals in response to the reference clock signal. N−1 of the pipeline control signals are generated in cascade from preceding pipeline control signals, and an (n)th pipeline control signal is generated directly from the reference clock signal. The control signal generating circuit provides the n pipeline control signals to the n pipe register, so that the total transmission time from the input terminals to the output terminals is minimal. Accordingly, the device can output the valid data within the shortest time by generating pipeline control signals of each stage with a minimum margin for possible changes of a temperature and power supply voltage.

Abstract translation: 高速流水线装置包括在输入端子和输出端子之间级联连接的n条数据路径电路。 N个数据传送电路具有传输时间{T 1 ，。 。 。 ，Tn}，每个小于参考时钟信号的周期P，至少一个传输时间与另一个不同。 N个管路寄存器连接到数据路径电路的输入端，以锁存从前一级或输入端传来的数据。 控制信号发生电路响应于参考时钟信号产生n个流水线控制信号。 从先前的流水线控制信号级联产生流水线控制信号的N-1，并且从参考时钟信号直接生成第（n）个流水线控制信号。 控制信号发生电路向n管寄存器提供n个流水线控制信号，使得从输入端到输出端的总传输时间最小。 因此，设备可以在最短时间内通过产生每个级的流水线控制信号来输出有效数据，并具有可能的温度和电源电压变化的最小余量。

公开(公告)号：US06633993B2

公开(公告)日：2003-10-14

申请号：US10051051

申请日：2002-01-22

Applicant: James A. Wilson ,  Robert F. Netting ,  Peter Des Rosier

Inventor： James A. Wilson ,  Robert F. Netting ,  Peter Des Rosier

IPC: G06F104

CPC classification number: G06F1/08

Abstract: A method and apparatus for limiting a processor clock frequency includes an overclocking prevention circuit. The overclocking prevention circuit includes a frequency limiting circuit having programmable fusible elements. The frequency limiting circuit outputs a signal identifying a maximum processor clock frequency based on the state of each of the fusible elements. A comparator circuit compares a selected processor clock frequency to the maximum processor clock frequency to determine if the selected processor clock frequency is permitted. If the selected processor clock frequency is not permitted, then the processor is not allowed to operate at the selected clock frequency.

Abstract translation: 用于限制处理器时钟频率的方法和装置包括超频防止电路。 超频防止电路包括具有可编程可熔元件的频率限制电路。 频率限制电路基于每个可熔元件的状态输出识别最大处理器时钟频率的信号。 比较器电路将所选择的处理器时钟频率与最大处理器时钟频率进行比较，以确定所选择的处理器时钟频率是否被允许。 如果所选择的处理器时钟频率不被允许，则处理器不允许以选定的时钟频率工作。

公开(公告)号：US06633992B1

公开(公告)日：2003-10-14

申请号：US09476412

申请日：1999-12-30

Applicant: Eitan Rosen

Inventor： Eitan Rosen

IPC: G06F104

CPC classification number: G06F1/04 ,  H03K19/0963

Abstract: A circuit has at least one data input, an enable input, a clock input, and an output. In one embodiment, the circuit is configured to perform a pre-charge function before an evaluate function in response to the enable input.

Abstract translation: 电路具有至少一个数据输入，使能输入，时钟输入和输出。 在一个实施例中，电路被配置为在响应于使能输入的评估功能之前执行预充电功能。

公开(公告)号：US06629253B1

公开(公告)日：2003-09-30

申请号：US09475735

申请日：1999-12-30

Applicant: Todd M. Witter ,  Aditya Sreenivas ,  Kim Meinerth

Inventor： Todd M. Witter ,  Aditya Sreenivas ,  Kim Meinerth

IPC: G06F104

CPC classification number: G06F3/14

Abstract: A method and apparatus for managing overlay data requests are disclosed. One embodiment of an apparatus includes a request unit and a timer. A request is made by a graphics controller to the request unit for a line of overlay data. The request unit divides the request from the graphics controller into a series of smaller requests. The smaller requests are issued to a memory controller. Delays are inserted between each of the smaller requests in order to allow other system resources to more easily gain access to memory.

Abstract translation: 公开了一种用于管理覆盖数据请求的方法和装置。 装置的一个实施例包括请求单元和定时器。 图形控制器向请求单元请求一行覆盖数据。 请求单元将请求从图形控制器分成一系列较小的请求。 向内存控制器发出较小的请求。 在每个较小的请求之间插入延迟，以便允许其他系统资源更容易地访问内存。

公开(公告)号：US06622254B1

公开(公告)日：2003-09-16

申请号：US09577682

申请日：2000-05-22

Applicant: Jeffrey Kao

Inventor： Jeffrey Kao

IPC: G06F104

CPC classification number: G06F1/04

Abstract: The invention provides a method of automatically overclocking CPUs for a computer system by using a frequency generator with functions of tuning frequency and monitoring, and applying a numeric method to get the frequency for booting a computer system. When a computer system is powered on and enters the overclocking process, the built-in parameters storing booting settings are loaded and backed up to be referenced in the next trial of booting. The frequency of overclocking is calculated by a numeric method according to the highest frequency generated by the frequency generator and the frequency of front side bus of the system. The built-in parameters are then stored to boot up a computer system at next time. Once the configuration of the computer system is changed, the values of parameters are invalid and need to be recalculated by entering the overclocking process. Using this automatic method, overclocking can be done in a shorter time than overclocking manually.

Abstract translation: 本发明提供一种通过使用具有调谐频率和监视功能的频率发生器自动超频计算机系统的CPU的方法，并且应用数字方法来获得引导计算机系统的频率。 当计算机系统通电并进入超频过程时，存储引导设置的内置参数将被加载并备份，以便在下次的引导尝试中引用。 根据频率发生器产生的最高频率和系统前端总线的频率，通过数字方法计算超频频率。 然后存储内置参数以便下次启动计算机系统。 一旦更改了计算机系统的配置，参数值无效，需要通过输入超频进程重新计算。 使用这种自动方法，可以在比手动进行的超频更短的时间内完成超频。

公开(公告)号：US06611922B2

公开(公告)日：2003-08-26

申请号：US09370863

申请日：1999-08-09

Applicant: H. Kurtulus Ozcetin ,  Simon H. Lightbody ,  Peter M. Van Doorn ,  Rene T. Jonker

Inventor： H. Kurtulus Ozcetin ,  Simon H. Lightbody ,  Peter M. Van Doorn ,  Rene T. Jonker

IPC: G06F104

CPC classification number: G06F1/14 ,  H04J3/0638

Abstract: A time synchronization device and method is provided for synchronizing an internal clock of the power monitor. The internal clock may be adjusted to a periodically stable frequency according to a calculated counting error. Also, a time of the internal clock may be synchronized to a universal time, the time of the internal clock advancing at a determined rate. The determined rate may be adjusted if the internal time differs from the universal time plus a processing time.

Abstract translation: 提供了一种用于同步功率监视器的内部时钟的时间同步装置和方法。 可以根据计算的计数误差将内部时钟调整到周期性稳定的频率。 此外，内部时钟的时间可以与通用时间同步，内部时钟以确定的速率前进。 如果内部时间不同于通用时间加上处理时间，则可以调整确定的速率。

公开(公告)号：US06597226B1

公开(公告)日：2003-07-22

申请号：US09615619

申请日：2000-07-13

Applicant: Tom Jon Eade ,  Brian Keith Owens

Inventor： Tom Jon Eade ,  Brian Keith Owens

IPC: G06F104

CPC classification number: H04B15/04 ,  G06F1/08 ,  H04B2215/064 ,  H04B2215/067

Abstract: The invention provides an ASIC architecture that incorporates an SSCG module therein and that utilizes both a frequency modulated clock signal and a pure clock signal, where both clock signals are substantially synchronized and where the ASIC architecture minimizes the number of pins and silicon area needed to provide the dual clock signals. Additionally, because the clock signals are derived from the same externally generated clock signal and are received into the ASIC through the same clock input buffer, the clock signals on both branch paths will be substantially synchronized, thereby reducing drift, skew or delay errors in the clock I/O buffers, between the various sections of the integrated circuit and/or between the various components coupled to, or part of the electronic device in which the integrated circuit is a part.

Abstract translation: 本发明提供了一种ASIC结构，其中并入SSCG模块，并利用频率调制时钟信号和纯时钟信号两者，其中两个时钟信号基本上是同步的，而ASIC架构最大限度地减少了提供的引脚数量和硅面积 双时钟信号。 另外，由于时钟信号是从相同的外部产生的时钟信号导出的，并且通过相同的时钟输入缓冲器被接收到ASIC中，两个分支路径上的时钟信号将基本上同步，从而减少了在 时钟I / O缓冲器，集成电路的各个部分之间和/或耦合到集成电路的一部分的电子设备的一部分之间。

公开(公告)号：US06594773B1

公开(公告)日：2003-07-15

申请号：US09511457

申请日：2000-02-23

Applicant: Rafael S. Lisitsa ,  George H. J. Shaw ,  Dale A. Sather ,  Bryan A. Woodruff ,  Costin Hagiu

Inventor： Rafael S. Lisitsa ,  George H. J. Shaw ,  Dale A. Sather ,  Bryan A. Woodruff ,  Costin Hagiu

IPC: G06F104

CPC classification number: H04N21/4307 ,  H04N21/4143 ,  H04N21/4302

Abstract: Frame based streaming data is controlled through a reconfigurable graph of processing modules. A client specifies overall goals for the graph. A graph manager constructs the graph as a sequence of interconnected modules for processing the data, in response to the capabilities of modules within the graph and the overall goals, and divides the graph into time domains each having one or more modules, pipes each having one or more modules, and a control mechanism is used that eliminates components unnecessary to the overall operation of the graph and that provides synchronization between time domains using time translation tables or timing correlation tables. The graph manager adaptively controls graphs that have a low latency requirement.

Abstract translation: 基于帧的流数据通过处理模块的可重构图进行控制。 客户指定图表的总体目标。 图形管理器将图形构建为用于处理数据的互连模块的序列，以响应于图中的模块的能力和总体目标，并且将图划分成具有一个或多个模块的时域，每个管具有一个或多个模块 或更多的模块，并且使用控制机制，其消除了图形的整体操作所不需要的组件，并且使用时间转换表或定时相关表在时域之间提供同步。 图形管理器自适应地控制具有低延迟要求的图形。

公开(公告)号：US06578156B1

公开(公告)日：2003-06-10

申请号：US09479443

申请日：2000-01-07

Applicant: Natsuki Sugita

Inventor： Natsuki Sugita

IPC: G06F104

CPC classification number: H03K17/164 ,  H03K17/167

Abstract: An output drive circuit of an output buffer circuit has a signal output line and first, second and third switching circuits connected to the signal output line at different locations thereof. Each of the first, second and third switching circuits includes one of first switching devices connected between a power source line and the signal output line, and one of second switching devices connected between the signal output line and a ground line. Each of the first, second and third switching circuits includes one of first control signal lines that turn on and off the first switching devices, respectively, and one of second control signal lines that turn on and off the second switching devices, respectively. Drivabilities of the first and/or the second switching devices in the switching circuits are set to gradually increase in a specified order.

Abstract translation: 输出缓冲电路的输出驱动电路具有信号输出线，并且在其不同位置连接到信号输出线的第一，第二和第三开关电路。 第一，第二和第三开关电路中的每一个包括连接在电源线和信号输出线之间的第一开关装置和连接在信号输出线与接地线之间的第二开关装置中的一个。 第一，第二和第三开关电路中的每一个分别包括分别接通和断开第一开关器件的第一控制信号线之一和分别导通和关断第二开关器件的第二控制信号线之一。 开关电路中的第一开关器件和/或第二开关器件的驱动能力被设定为以指定的顺序逐渐增加。

公开(公告)号：US06560715B1

公开(公告)日：2003-05-06

申请号：US09432972

申请日：1999-11-03

Applicant: Jean-Pierre Bourdillat ,  Michel Richy

Inventor： Jean-Pierre Bourdillat ,  Michel Richy

IPC: G06F104

CPC classification number: G06F9/3842 ,  G06F15/7842

Abstract: For triggering actions synchronous with a system clock in an electronic system comprising a management processor, a program memory and peripheral units, the sequencer comprises: an instruction register including a date field for containing an instruction execution date, an instruction code field and a data field, means for loading the instruction register from the program memory via a DMA channel, a comparator receiving a current date obtained from the system clock and the execution date contained in the date field of the instruction register, and a control logic unit for decoding the contents of the instruction code and data fields of the instruction register and triggering actions deduced from such decoding at the time the comparator shows that the current date has reached the execution date in the peripheral units and without intervention by the management processor.

Abstract translation: 为了与包括管理处理器，程序存储器和外围单元的电子系统中的系统时钟同步的触发动作，定序器包括：指令寄存器，包括用于包含指令执行日期的日期字段，指令代码字段和数据字段 ，用于经由DMA通道从程序存储器加载指令寄存器的装置，接收从系统时钟获得的当前日期的比较器和包含在指令寄存器的日期字段中的执行日期的装置，以及用于对内容进行解码的控制逻辑单元 指示寄存器的指令代码和数据字段以及在比较器显示当前日期已经到达外围单元的执行日期并且没有管理处理器干预时从这种解码推导的触发动作。