公开(公告)号：US20150179465A1

公开(公告)日：2015-06-25

申请号：US14637260

申请日：2015-03-03

Applicant: LAM Research Corporation

Inventor： Harmeet Singh ,  Alex Paterson

IPC: H01L21/3065 ,  H01L21/3213 ,  H01L21/311

CPC classification number: H01L21/67213 ,  H01J37/32 ,  H01J37/32422 ,  H01J37/3244 ,  H01J37/32458 ,  H01J37/32623 ,  H01J2237/327 ,  H01J2237/3341 ,  H01L21/02057 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/67069 ,  H01L43/12

Abstract: The disclosed embodiments relate to methods and apparatus for removing material from a substrate. In various implementations, conductive material is removed from a sidewall of a previously etched feature such as a trench, hole or pillar on a semiconductor substrate. In practicing the techniques herein, a substrate is provided in a reaction chamber that is divided into an upper plasma generation chamber and a lower processing chamber by a corrugated ion extractor plate with apertures therethrough. The extractor plate is corrugated such that the plasma sheath follows the shape of the extractor plate, such that ions enter the lower processing chamber at an angle relative to the substrate. As such, during processing, ions are able to penetrate into previously etched features and strike the substrate on the sidewalls of such features. Through this mechanism, the material on the sidewalls of the features may be removed.

公开(公告)号：US20150060404A1

公开(公告)日：2015-03-05

申请号：US14016994

申请日：2013-09-03

Applicant: Lam Research Corporation

Inventor： Rajinder Dhindsa ,  Harmeet Singh

IPC: H01J37/32 ,  H01L21/67

CPC classification number: H01J37/32137 ,  H01J37/32082 ,  H01J37/32449 ,  H01J37/32532 ,  H01J37/32623 ,  H01J37/32633 ,  H01J37/32816 ,  H01J37/32834

Abstract: A plasma processing system and method includes a processing chamber, and a plasma processing volume included therein. The plasma processing volume having a volume less than the processing chamber. The plasma processing volume being defined by a top electrode, a substrate support surface opposing the surface of the top electrode and a plasma confinement structure including at least one outlet port. A conductance control structure is movably disposed proximate to the at least one outlet port and capable of controlling an outlet flow through the at least one outlet port between a first flow rate and a second flow rate, wherein the conductance control structure controls the outlet flow rate and an at least one RF source is modulated and at least one process gas flow rate is modulated corresponding to a selected processing state set by the controller during a plasma process.

Abstract translation: 等离子体处理系统和方法包括处理室和其中包括的等离子体处理体积。 等离子体处理体积的体积小于处理室。 等离子体处理体积由顶部电极，与顶部电极的表面相对的衬底支撑表面和包括至少一个出口的等离子体限制结构限定。 导电控制结构可移动地设置在靠近所述至少一个出口端口处并且能够控制通过所述至少一个出口端口的出口流在第一流量和第二流量之间，其中所述电导控制结构控制所述出口流量 并且至少一个RF源被调制，并且至少一个处理气体流量是在等离子体处理期间由控制器设定的选择的处理状态调制的。

公开(公告)号：US20140302680A1

公开(公告)日：2014-10-09

申请号：US13916318

申请日：2013-06-12

Applicant: Lam Research Corporation

Inventor： Harmeet Singh ,  Thorsten Lill ,  Vahid Vahedi ,  Alex Paterson ,  Monica Titus ,  Gowri Kamarthy

IPC: H01L21/3065 ,  H01L21/67

CPC classification number: H01L21/67069 ,  H01J37/32009 ,  H01J37/32422 ,  H01J37/3244 ,  H01J37/32633 ,  H01J37/32715 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32136

Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. Where multiple plasma grids are used, one or more of the grids may be movable, allowing for tenability of the plasma conditions in at least the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber.

Abstract translation: 这里公开的实施例涉及用于蚀刻半导体衬底的改进的方法和设备。 等离子体栅格组件位于反应室中，以将室分成上部和下部子室。 等离子体栅格组件可以包括具有特定纵横比的槽的一个或多个等离子体栅格，其允许某些物质从上部子室通到下部子室。 在使用多个等离子体栅格的情况下，一个或多个栅格可以是可移动的，允许至少在下部子室中的等离子体条件的稳定性。 在一些情况下，在上部子室中产生电子 - 离子等离子体。 使其通过栅格到下部子室的电子在它们通过时被冷却。 在某些情况下，这导致下部子室中的离子离子等离子体。

公开(公告)号：US20140110060A1

公开(公告)日：2014-04-24

申请号：US14139238

申请日：2013-12-23

Applicant: Lam Research Corporation

Inventor： Keith William Gaff ,  Harmeet Singh ,  Keith Comendant ,  Vahid Vahedi

IPC: H01J37/20

CPC classification number: H01J37/20 ,  H01L21/67248 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A plasma etching system having a substrate support assembly with multiple independently controllable heater zones. The plasma etching system is configured to control etching temperature of predetermined locations so that pre-etch and/or post-etch non-uniformity of critical device parameters can be compensated for.

Abstract translation: 一种等离子体蚀刻系统，具有具有多个可独立控制的加热器区域的基板支撑组件。 等离子体蚀刻系统被配置为控制预定位置的蚀刻温度，从而可以补偿临界器件参数的预蚀刻和/或蚀刻后不均匀性。

公开(公告)号：US20140096909A1

公开(公告)日：2014-04-10

申请号：US14101782

申请日：2013-12-10

Applicant: Lam Research Corporation

Inventor： Harmeet Singh ,  Keith Gaff ,  Neil Benjamin ,  Keith Comendant

IPC: H01L21/67

CPC classification number: H01L21/67103 ,  C23C14/50 ,  C23C14/541 ,  C23C16/4586 ,  C23C16/46 ,  C23C16/509 ,  H01J37/32091 ,  H01J37/32724 ,  H01J2237/327 ,  H01J2237/332 ,  H01J2237/3321 ,  H01J2237/3323 ,  H01J2237/334 ,  H01J2237/3342 ,  H01J2237/3343 ,  H01L21/02274 ,  H01L21/0262 ,  H01L21/28556 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32136 ,  H01L21/67109 ,  H01L21/67248 ,  H01L21/6831 ,  H05B1/0233 ,  H05B3/00 ,  H05B3/26 ,  Y10T29/49083 ,  Y10T29/49099

Abstract: A heating plate of a semiconductor substrate support for supporting a semiconductor substrate in a plasma processing chamber includes a first layer with an array of heater zones operable to tune a spatial temperature profile on the semiconductor substrate, and a second layer with one or more primary heaters to provide mean temperature control of the semiconductor substrate. The heating plate can be incorporated in a substrate support wherein a switching device independently supplies power to each one of the heater zones to provide time-averaged power to each of the heater zones by time divisional multiplexing of the switches.

Abstract translation: 用于在等离子体处理室中支撑半导体衬底的半导体衬底支撑体的加热板包括具有加热器阵列阵列的第一层，其可操作以调节半导体衬底上的空间温度分布，以及具有一个或多个初级加热器的第二层 以提供半导体衬底的平均温度控制。 加热板可以结合在基板支撑件中，其中开关装置独立地向每个加热器区域供电，以通过开关的时分复用为每个加热器区域提供时间平均的功率。