-
公开(公告)号：US20220122546A1
公开(公告)日：2022-04-21
申请号：US17563375
申请日：2021-12-28
IPC: G09G3/3266 , G09G3/3233 , G09G3/3291
Abstract: A display panel and a display device are disclosed, the display panel includes a plurality of display regions, a peripheral region surrounding the plurality of display regions, a plurality of light-emission control scan driving circuits provided in the peripheral region, a first start signal line, and a second start signal line. The first start signal line is different from the second start signal line, the plurality of display regions include a first display region and a second display region, the plurality of light-emission control scan driving circuits include a first light-emission control scan driving circuit and a second light-emission control scan driving circuit, the first start signal line is configured to provide a first start signal to the first light-emission control scan driving circuit, and the second start signal line is configured to provide a second start signal to the second light-emission control scan driving circuit.
-
公开(公告)号：US20210407426A1
公开(公告)日：2021-12-30
申请号：US16771446
申请日：2019-08-21
Inventor： Chao ZENG , Weiyun HUANG , Yue LONG , Yao HUANG , Meng LI
IPC: G09G3/3266
Abstract: A display substrate and a manufacturing method thereof, and a display device are provided. The display substrate includes a base substrate, including a pixel array region and a peripheral region; and a first scan driving circuit, a plurality of power lines, a first signal line group, and a second signal line group. The first scan driving circuit includes a plurality of cascaded first shift registers; the plurality of power lines are configured to provide a plurality of power voltages to the plurality of cascaded first shift registers in the first scan driving circuit; the first signal line group includes at least one timing signal line; the second signal line group includes a first trigger signal line configured to provide a first trigger signal to a first-stage first shift register; and the first trigger signal line is between the plurality of power lines and the pixel array region.
-
公开(公告)号：US20210407425A1
公开(公告)日：2021-12-30
申请号：US16766094
申请日：2019-07-01
Inventor： Weiyun HUANG , Libin LIU , Chao ZHENG , Yao HUANG , Meng LI , Yue LONG
IPC: G09G3/3266 , G09G3/00
Abstract: A display panel, a display device and a driving method are disclosed, the display panel includes a plurality of display regions, the plurality of display regions include a first display region and a second display region, the first display region includes rows of first pixel units, the second display region includes rows of second pixel units; the display panel further includes a first light-emission control scan driving circuit for controlling the rows of first pixel units to emit light, and a second light-emission control scan driving circuit for controlling the rows of second pixel units to emit light, and the driving method includes: providing a first start signal to the first light-emission control scan driving circuit, and providing a second start signal to the second light-emission control scan driving circuit; the second start signal and the first start signal are applied independently, respectively.
-
公开(公告)号：US20210335245A1
公开(公告)日：2021-10-28
申请号：US17259702
申请日：2020-06-24
IPC: G09G3/3233 , G09G3/3275 , G09G3/32
Abstract: A method for controlling a charging time of a display panel includes: during t0+kΔt in a (k+1)-th blanking time, writing a data voltage to a gate of a driving transistor, and detecting a voltage Vk_(j,i) of a second electrode of the driving transistor; during a t0+(k+r)Δt in a (k+1+r)-th blanking time, writing the data voltage to the gate of the driving transistor, and detecting a voltage Vk+i_(j,i) of the second electrode of the driving transistor; determining whether ΔVj,i=Vk+1_ji−Vk_ji is less than or equal to a target voltage difference VT; if ΔVj,i≤VT, taking the T=t0+kΔt as an expected charging time of a sub-pixel; if ΔVj,i>VT, cyclically performing the charging step described above to obtain ΔVj,i=Vk+p+1_(j,i)−Vk+p_(j,i), and comparing ΔVj,i with the target voltage difference VT, until ΔVj,i≤VT, taking t0+(k+p+r−1)Δt as the expected charging time of the sub-pixel. p is taken from 1, and increases by 1 for each cycle.
-
Patent Agency Ranking
公开(公告)号：US20210202679A1
公开(公告)日：2021-07-01
申请号：US16977928
申请日：2019-11-29
Inventor： Meng LI , Zhongyuan WU , Yongqian LI , Can YUAN , Zhidong YUAN , Xuehuan FENG , Lang LIU , Dacheng ZHANG
IPC: H01L27/32 , H01L51/52 , H01L51/56 , G09G3/3233
Abstract: A display substrate and a manufacturing method thereof and a display device are provided. The display substrate includes a base substrate and sub-pixels on the base substrate. The sub-pixels are arranged in a sub-pixel array. At least one sub-pixel includes a first transistor, a second transistor, a third transistor and a storage capacitor. The first electrode of the third transistor is electrically connected to an active layer of the third transistor through a first via hole, and the first electrode of the third transistor is configured to be electrically connected to the light emitting element through a second via hole; the first via hole and the second via hole are at least partially overlapped with each other in a direction perpendicular to the base substrate.
-
公开(公告)号：US20210202605A1
公开(公告)日：2021-07-01
申请号：US16977512
申请日：2019-11-29
Inventor： Zhongyuan WU , Yongqian LI , Can YUAN , Meng LI , Zhidong YUAN , Dacheng ZHANG , Lang LIU
IPC: H01L27/32
Abstract: A display substrate and a display device are provided. The display substrate includes sub-pixels which are arranged in a sub-pixel array in a first direction and a second direction. At least one sub-pixel includes a first transistor, a second transistor, a third transistor, and a storage capacitor. An active layer of the third transistor includes a body region and a first via hole region successively arranged in the first direction and electrically connected with each other; a first electrode of the third transistor is electrically connected to the first via hole region through a first via hole which is shifted in the second direction with respect to the body region, allowing the active layer incudes a first active layer side connecting the body region and the first via hole region; an extension direction of the first active layer side intersects with both the first direction and the second direction.
-
公开(公告)号：US20210193001A1
公开(公告)日：2021-06-24
申请号：US16072049
申请日：2018-01-08
Inventor： Xuehuan FENG , Xing ZHANG , Qi HU , Pan XU , Yongqian LI , Meng LI , Zhidong YUAN , Zhenfei CAI , Can YUAN
Abstract: The present application discloses a shift register, a gate driving circuit and a driving method thereof, and a display apparatus. The shift register includes an input sub-circuit, an output sub-circuit, a reset control sub-circuit, a pull-up node reset sub-circuit, and an output signal reset sub-circuit; the input sub-circuit is configured to pre-charge the pull-up node under the control of a signal input to the first signal input terminal; the output sub-circuit is configured to output, through the signal output terminal, a signal input to the first clock signal input terminal under the control of a potential of the pull-up node; the reset control sub-circuit is configured to control, under the control of a reset signal input to the second signal input terminal, whether the pull-up node reset sub-circuit and the output signal reset sub-circuit operate to reset the pull-up node and the signal output terminal, respectively.
-
公开(公告)号：US20210167162A1
公开(公告)日：2021-06-03
申请号：US17040260
申请日：2019-11-29
Inventor： Zhongyuan WU , Yongqian LI , Can YUAN , Meng LI , Zhidong YUAN , Xuehuan FENG , Lang LIU , Dacheng ZHANG
IPC: H01L27/32
Abstract: The present disclosure relates to the field of display technologies, and provides an array substrate, a manufacturing method thereof, and a display panel. In the array substrate, a substrate is provided with a first transistor and a second transistor, a first electrode of the first transistor is electrically connected to a gate of the second transistor; a conductive layer is disposed on the substrate, and includes a first conductor portion, a first semiconductor portion, a second conductor portion that are sequentially connected along a first direction; a first gate insulating layer is disposed on a side of the conductive layer away from the substrate; a first gate layer is disposed on a side of the first gate insulating layer away from the substrate to form the gate of the second transistor; a dielectric layer is disposed on the substrate to cover a part of the first conductor portion, a part of the second conductor portion and a part of the first gate layer, and an orthographic projection of a first via hole disposed on the dielectric layer on the substrate overlaps with orthographic projections of at least a part of the first conductor portion, at least a part of the second conductor portion and the first gate layer on the substrate; and a first source/drain layer is disposed on a side of the dielectric layer away from the substrate to cover the first via hole.
-
99.发明申请公开(公告)号：US20190386033A1
公开(公告)日：2019-12-19
申请号：US16440615
申请日：2019-06-13
Inventor： Meng LI , Yongqian LI , Min HE
IPC: H01L27/12 , H01L27/32 , G09G3/3291 , G09G3/3266 , G09G3/3233
Abstract: Embodiments of the present disclosure provide an OLED array substrate, a method for fabricating an OLED array substrate, an OLED pixel circuit, an OLED array substrate including the OLED pixel circuit, and a display device including the OLED array substrate. The OLED array substrate includes a substrate, an OLED arranged on the substrate, and a photosensor positioned between the OLED and the substrate. The photosensor includes a first electrode, a photosensitive layer, and a second electrode sequentially arranged from bottom to top. The OLED includes an anode, an organic light-emitting layer, and a cathode sequentially arranged from bottom to top. The anode includes a first portion and a second portion.
-
-
-
-
-
-
-
-
Search Results
99
records
(took 0.026 seconds)
