公开(公告)号：US5459642A

公开(公告)日：1995-10-17

申请号：US253980

申请日：1994-06-03

Applicant: D. Joe Stoddard

Inventor： D. Joe Stoddard

IPC: H01G2/06 ,  H01G4/252 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/00 ,  H05K3/34

CPC classification number: H05K3/3442 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/114 ,  H05K2201/0792 ,  H05K2201/09772 ,  H05K2201/10636 ,  H05K3/0094 ,  Y02P70/611 ,  Y02P70/613

Abstract: A capacitor mounting structure for printed circuit boards wherein the capacitor includes first and second terminals which are connected to first and second conductor planes in the printed circuit board. Three vias are mounted in the printed circuit board in a position to be aligned with the middle of the capacitor. A first conductor pad is mounted underneath one end of the capacitor and includes spaced apart extension portions which electrically attach to the first and third via. A second conductor pad is mounted under the other end of the capacitor and includes a central extension portion which attaches to the second or middle via. In this manner, the region available for generation of parasitic inductance is minimized thereby increasing the operating efficiency of the capacitor.

Abstract translation: 一种用于印刷电路板的电容器安装结构，其中电容器包括连接到印刷电路板中的第一和第二导体平面的第一和第二端子。 三个通孔安装在印刷电路板中与电容器中间对准的位置。 第一导体焊盘安装在电容器的一端下方，并且包括电连接到第一和第三通孔的间隔开的延伸部分。 第二导体焊盘安装在电容器的另一端下方，并且包括连接到第二或中间通孔的中心延伸部分。 以这种方式，可用于产生寄生电感的区域被最小化，从而提高了电容器的工作效率。

公开(公告)号：US5455907A

公开(公告)日：1995-10-03

申请号：US119718

申请日：1993-09-10

Applicant: Randall L. Hess ,  Gaines C. Teague ,  Patrick R. Cooper ,  Daniel B. Reents ,  Hung Q. Le

Inventor： Randall L. Hess ,  Gaines C. Teague ,  Patrick R. Cooper ,  Daniel B. Reents ,  Hung Q. Le

IPC: G06F3/033 ,  G06F3/048 ,  G06F15/00

CPC classification number: G06F3/04883

Abstract: A computer system with a digitizer based screen display in which the digitizer data is buffered through a first-in first-out memory (FIFO). The processor is only interrupted when a full digitizer data packet is available in the FIFO, rather than being interrupted on each data byte available in the FIFO. The FIFO can hold multiple digitizer data packets, so that data is not lost should the processor in the computer system be unable to immediately handle these digitizer data packets. The system also provides a filter in a separate controller that examines each digitizer data packet to determine if the pen is in a predefined screen location that performs a prespecified function. If so, rather than pass the digitizer data packet to the system processor through the FIFO, the command is passed through a separate register to the processor based on the "hotspot" touched on the screen.

Abstract translation: 一种具有基于数字化仪的屏幕显示的计算机系统，其中数字转换器数据通过先进先出存储器（FIFO）进行缓冲。 只有当FIFO中有一个完整的数字转换器数据包可用时，才会中断处理器，而不是在FIFO中可用的每个数据字节中断处理器。 FIFO可以容纳多个数字转换器数据包，以便计算机系统中的处理器无法立即处理这些数字化数据包时数据不会丢失。 该系统还在单独的控制器中提供一个过滤器，该过滤器检查每个数字化仪数据包，以确定笔是否在执行预定功能的预定屏幕位置。 如果是，则不是通过FIFO将数字转换器数据包传递给系统处理器，而是根据触摸屏幕上的“热点”将命令传递给处理器。

公开(公告)号：US5455757A

公开(公告)日：1995-10-03

申请号：US188484

申请日：1994-01-28

Applicant: Hai N. Nguyen ,  James S. Dinh

Inventor： Hai N. Nguyen ,  James S. Dinh

IPC: H02M3/335

CPC classification number: H02M3/33569

Abstract: A power converter including a complementary regeneration circuit for eliminating oscillations and conserving leakage energy to increase the efficiency of a flyback power converter. The complementary regeneration circuit includes a regeneration capacitor, a regeneration switch, a diode and appropriate timing circuitry to switch the regeneration capacitor in and out of the circuit at the appropriate times. Due to the operation of the regeneration switch, the capacitance of the regeneration capacitor is much larger than a typical snubber/clamp capacitor, so that it overdamps the circuit eliminating voltage overshoot typically appearing across the primary switch. The regeneration capacitor charges with regeneration energy and drives negative current into the primary inductor, holding the voltage across the primary switch constant when the secondary current goes to zero. When the regeneration switch is turned off, the negative current in the primary inductor drains the capacitance in the primary switch, which activates the inherent diode of the primary switch causing low voltage across the primary switch when it is turned on. A simple resistor or transistor circuit may be added between the input voltage and the PWM timing circuit to change the frequency of operation to compensate the regeneration energy for changes in the input voltage. Similarly, a resistive element coupled between the PWM timing circuit and an auxiliary voltage having a voltage proportional to the output voltage changes the operating frequency to compensate the regeneration energy for changes in the output voltage.

Abstract translation: 一种功率转换器，包括用于消除振荡并且节省泄漏能量以提高回扫功率转换器的效率的互补再生电路。 补充再生电路包括再生电容器，再生开关，二极管和适当的定时电路，用于在适当的时间将再生电容器进入和退出电路。 由于再生开关的操作，再生电容器的电容远远大于典型的缓冲器/钳位电容器，因此其过电流消除了通常出现在主开关上的电压过冲。 再生电容器用再生能量充电，并将负电流驱动到主电感器中，当次级电流变为零时，保持主开关两端的电压恒定。 当再生开关关闭时，初级电感器中的负电流消耗了初级开关中的电容，当初级开关导通时，初级开关的固有二极管在主开关两端产生低电压。 可以在输入电压和PWM定时电路之间添加简单的电阻器或晶体管电路，以改变操作频率以补偿用于输入电压变化的再生能量。 类似地，耦合在PWM定时电路和具有与输出电压成正比的电压的辅助电压之间的电阻元件改变工作频率，以补偿再生能量以改变输出电压。

公开(公告)号：US5450609A

公开(公告)日：1995-09-12

申请号：US163395

申请日：1993-12-06

Applicant: Stephen M. Schultz ,  Richard A. Ewert

Inventor： Stephen M. Schultz ,  Richard A. Ewert

IPC: G06F11/34

CPC classification number: G06F11/3485 ,  G06F11/3409 ,  G06F11/348 ,  G06F2201/81 ,  G06F2201/88

Abstract: A system for monitoring performance of an intelligent array expansion system includes a controller for communicating with a host computer and associated intelligent array expansion systems, each of which has a plurality of fixed disk drives. The controller incorporates firmware to monitor a plurality of predetermined performance data, such data being thereafter stored in information storage devices. At the same time counts are maintained for selected parameters which are of interest to a systems manager. Such counts and the performance data are stored for each one of a plurality of preselected intervals, and an indication or warning is given to the systems manager when performance data, or when a selected parameter exceeds a preselected threshold.

Abstract translation: 用于监视智能阵列扩展系统的性能的系统包括用于与主计算机和相关联的智能阵列扩展系统通信的控制器，每个智能阵列扩展系统具有多个固定磁盘驱动器。 该控制器包含固件以监视多个预定的演奏数据，此后将数据存储在信息存储装置中。 同时，为系统管理员感兴趣的所选参数保持计数。 对于多个预先选择的间隔中的每一个存储这样的计数和性能数据，并且当执行数据或当所选择的参数超过预选阈值时向系统管理员提供指示或警告。

公开(公告)号：US5446619A

公开(公告)日：1995-08-29

申请号：US106051

申请日：1993-08-12

Applicant: Roberta M. Madsen ,  David A. Moore ,  Brian J. Perona

Inventor： Roberta M. Madsen ,  David A. Moore ,  Brian J. Perona

IPC: G06F1/20 ,  H05K7/20

CPC classification number: G06F1/20

Abstract: A card extender unit for a computer housing including first and second card extender sections which mount the card extender in position in the computer housing. The card extender includes a housing including first and second sections which support a printed circuit board having one or more high wattage, integrated circuits. One of the card extender sections includes a flow direction channel intake for directing air generated by an internal housing fan over one or more of the high wattage, integrated circuits mounted on the printed circuit board.

Abstract translation: 一种用于计算机外壳的卡片扩展器单元，包括第一和第二扩充器部分，其将卡延伸器安装在计算机外壳中的适当位置。 卡片延伸器包括壳体，该壳体包括支撑具有一个或多个高功率集成电路的印刷电路板的第一和第二部分。 卡片延伸部分之一包括用于将由内部壳体风扇产生的空气引导到安装在印刷电路板上的高瓦数，集成电路中的一个或多个上的流动方向通道入口。

公开(公告)号：US5446320A

公开(公告)日：1995-08-29

申请号：US825000

申请日：1992-01-24

Applicant: Donald G. Scharnberg ,  Patrick R. Cooper

Inventor： Donald G. Scharnberg ,  Patrick R. Cooper

IPC: G05F3/24 ,  H01H83/00 ,  G05F3/00

CPC classification number: G05F3/24

Abstract: A circuit for connecting the power supply output of a computer to ground when the system is shut down to counter adverse effects of backfeed voltage which includes a MOSFET between the power supply output and ground. In one embodiment the MOSFET is switched on by a signal that deactivates the system power supply. In an alternative embodiment, two MOSFETs are used. The first MOSFET is controlled directly by the power supply output and shorts the second MOSFET's gate to ground when the power supply output generates a significant voltage. If the second MOSFET's gate is grounded, the MOSFET deactivates and opens a circuit between the power supply output and ground. When the power supply is turned off, the second MOSFET activates and grounds the power supply output. A resistor between the power supply output and ground allows the power supply to generate five volts when the system is power cycled and deactivate the second MOSFET.

Abstract translation: 一种用于在系统关闭时将计算机的电源输出连接到地的电路，以抵抗包括电源输出和地之间的MOSFET的反馈电压的不利影响。 在一个实施例中，MOSFET由导通系统电源的信号导通。 在替代实施例中，使用两个MOSFET。 第一个MOSFET由电源输出直接控制，当电源输出产生一个明显的电压时，将第二个MOSFET的栅极短路到地。 如果第二个MOSFET的栅极接地，则MOSFET会在电源输出和地之间停用并打开一个电路。 当电源关闭时，第二个MOSFET激活并接地电源输出。 电源输出和地之间的电阻允许电源在系统上电循环时产生5伏特电压，并禁用第二个MOSFET。

公开(公告)号：US5444312A

公开(公告)日：1995-08-22

申请号：US878443

申请日：1992-05-04

Applicant: Ronald D. Noblett ,  Kurtis J. Bowman

Inventor： Ronald D. Noblett ,  Kurtis J. Bowman

IPC: H03G3/34 ,  H04B15/00

CPC classification number: H03G3/34

Abstract: A soft switching circuit gradually connects an audio signal to zero reference level to mute the audio signal, or connect a filter to enable the filter. A MOSFET is connected between the audio signal and the zero reference level. A resistor-capacitor circuit is connected to the gate of the MOSFET and receives the MUTE or FILTER* signal from the computer system. When the MUTE or FILTER* signal changes condition, the RC circuit provides a signal to the MOSFET gate that changes relatively gradually. Consequently, the drain-to-source resistance of the MOSFET also changes from short circuit to open circuit or vice versa relatively gradually.

Abstract translation: 软开关电路逐渐将音频信号连接到零参考电平以使音频信号静音，或连接滤波器以启用滤波器。 一个MOSFET连接在音频信号和零参考电平之间。 电阻电容电路连接到MOSFET的栅极，并从计算机系统接收MUTE或FILTER *信号。 当MUTE或FILTER *信号变化时，RC电路向MOSFET栅极提供相对逐渐变化的信号。 因此，MOSFET的漏极 - 源极电阻也从短路转为开路，反之亦然。

公开(公告)号：US5440751A

公开(公告)日：1995-08-08

申请号：US718805

申请日：1991-06-21

Applicant: Paul Santeler ,  Gary W. Thome

Inventor： Paul Santeler ,  Gary W. Thome

IPC: G06F12/08 ,  G06F13/28 ,  G06F13/42 ,  G06F5/06

CPC classification number: G06F13/28 ,  G06F13/4243 ,  G06F12/0879

Abstract: An apparatus which converts burst mode bus cycles into single cycle mode cycles and converts separate address and data strobe signals into a single address strobe in a computer system. The apparatus also receives an address strobe signal, a number of address signals and the length of the burst when a device begins a burst cycle. After the first cycle of the burst transfer is complete, the apparatus initiates each subsequent cycle comprising the burst transfer by incrementing the address signals and providing additional address strobe signals until the burst is complete. The logic also facilitates address pipelining by monitoring a next address signal generated by the device. The apparatus monitors the separate address strobe and data strobe signals and generates the single address strobe signal on the next clock cycle after the address and data strobe signals are asserted. If only the address strobe signal is asserted at the beginning of a cycle, then the single address strobe signal is asserted only after valid data is available on the bus and the data strobe signal is asserted. The apparatus also monitors next address signals generated by the device to facilitate pipelining.

Abstract translation: 将突发模式总线周期转换为单周期模式周期并将单独的地址和数据选通信号转换成计算机系统中的单个地址选通的装置。 当设备开始突发周期时，该设备还接收地址选通信号，多个地址信号和突发的长度。 在突发传送的第一周期完成之后，设备通过递增地址信号并提供附加的地址选通信号来启动包括突发传输的每个后续周期，直到突发完成。 该逻辑还通过监视由设备生成的下一个地址信号来促进地址流水线化。 该设备监视分离的地址选通和数据选通信号，并在地址和数据选通信号被置位之后的下一个时钟周期产生单个地址选通信号。 如果只有地址选通信号在一个周期的开头被断言，那么只有在总线上的有效数据可用并且数据选通信号有效之后，单个地址选通信号被置位。 该装置还监视由装置产生的下一个地址信号以便于流水线化。

公开(公告)号：US5440716A

公开(公告)日：1995-08-08

申请号：US145029

申请日：1993-10-28

Applicant: Stephen M. Schultz ,  David S. Schmenk ,  E. David Neufeld ,  David L. Grant ,  David L. Flower

Inventor： Stephen M. Schultz ,  David S. Schmenk ,  E. David Neufeld ,  David L. Grant ,  David L. Flower

IPC: G06F3/06 ,  G06F7/22

CPC classification number: G06F3/0601 ,  G06F11/1096 ,  G06F3/0613 ,  G06F3/0632 ,  G06F3/0689 ,  G06F2003/0692

Abstract: For use with a computer system having an intelligent mass storage disk array subsystem, including a microprocessor controller, a method for the distribution of data within the disk array based upon logical commands issued by the computer system. The disk controller reads a logical command and translates the commands into multiple drive specific commands, including drive physical parameter information such as head, sector and cylinder selection. The calculation of these physical parameters is based upon a number of factors including the operating system installed in the computer system, the type of interleave scheme, if any, specified by the computer system configuration, and disk specific parameters. The physical drive requests are then placed in a queue and executed by the microprocessor controller. The method also encompasses a method for creating a disk array configuration to be loaded on all disks within the array based on existing valid disk array information and configuration information maintained by the computer system.

Abstract translation: 用于具有包括微处理器控制器的智能大容量存储盘阵列子系统的计算机系统，基于由计算机系统发出的逻辑命令在盘阵列内分发数据的方法。 磁盘控制器读取逻辑命令并将命令转换为多个驱动器特定的命令，包括驱动器物理参数信息，如磁头，扇区和气缸选择。 这些物理参数的计算基于许多因素，包括安装在计算机系统中的操作系统，由计算机系统配置指定的交织方案的类型（如果有的话）以及盘特定参数。 然后将物理驱动器请求置于队列中并由微处理器控制器执行。 该方法还包括基于由计算机系统维护的现有有效磁盘阵列信息和配置信息来创建要加载到阵列内的所有磁盘上的磁盘阵列配置的方法。

公开(公告)号：US5320554A

公开(公告)日：1994-06-14

申请号：US955668

申请日：1992-10-02

Applicant: Raymond A. Freer ,  Joseph R. Allen ,  James A. Mouton

Inventor： Raymond A. Freer ,  Joseph R. Allen ,  James A. Mouton

IPC: H01R13/62 ,  H01R4/50

CPC classification number: H01R13/62

Abstract: An attachment unit interface electrical connector which includes a slide latch which is moveable between open and close positions utilizing a pivotally mounted tab member. The pivotally mounted tab member is mounted onto the slidably mounted latch so that the latch member is accessible even when the attachment unit interface female connector is attached to a male connector in an area of confinement.

Abstract translation: 附接单元接口电连接器，其包括滑动闩锁，滑动闩锁可利用枢转安装的突片构件在打开位置和关闭位置之间移动。 枢转安装的突片构件安装到可滑动地安装的闩锁上，使得即使当在限制区域中附接单元接口母连接器附接到阳连接器时，闩锁构件也可接近。