公开(公告)号：US11777489B1

公开(公告)日：2023-10-03

申请号：US17747387

申请日：2022-05-18

Applicant: Xilinx, Inc.

Inventor： Hari Bilash Dubey ,  Milind Goel ,  Venkata Siva Satya Prasad Babu Akurathi ,  Sabarathnam Ekambaram ,  Sasi Rama Subrahmanyam Lanka

IPC: H03K17/22 ,  H03K17/10 ,  H03K19/00 ,  H03K19/003

CPC classification number: H03K17/223 ,  H03K17/102 ,  H03K19/0013 ,  H03K19/00315

Abstract: A disclosed circuit arrangement detects the supply voltage level to the “device” (SoC, chip, SiP, etc.) and adjusts bias voltages to receiver and transmitter circuits of the device to levels suitable for the device in response to the supply voltage ramping-up during a power-on reset (“POR”) sequence. The circuitry holds the receiver output at a constant logic value while the supply voltage is ramping up and the POR signal is asserted. The disclosed circuitry also protects the transceiver as the voltage domain of the input signal is unknown and the voltage between any two terminals of a transistor of the transceiver cannot exceed a certain level.

公开(公告)号：US12153458B2

公开(公告)日：2024-11-26

申请号：US18082921

申请日：2022-12-16

Applicant: XILINX, INC.

Inventor： Sasi Rama Subrahmanyam Lanka ,  Vss Prasad Babu Akurathi ,  Hari Bilash Dubey

IPC: H03K17/687 ,  G05F1/56

Abstract: An input/output (I/O) buffer is implemented without an auxiliary power supply (VCCAUX). The input/output (I/O) buffer includes a connection to a VCCO power supply, a connection to a VCCINT power supply, a connection to a reference voltage, and a VCCO detection circuit coupled to a bias generation circuit. Further, the I/O buffer includes a transmitter circuit coupled to the bias generation circuit, and a receiver circuit coupled to an I/O pad.