Abstract:
Systems, devices, and circuits for source-synchronous memory interfaces are disclosed. For example, a device includes a first NAND gate with an input for receiving a serial mode enable signal. In addition, the device also includes a second NAND gate with an input for receiving a forwarded strobe signal and an input for receiving an output of the first NAND gate. The device also includes a third NAND gate with an input for receiving a data strobe signal, and an XNOR gate with an input for receiving an output of the second NAND gate and an input for receiving an output of the third NAND gate.
Abstract:
A method, non-transitory computer readable medium and circuit for gating a strobe (DQS) signal are disclosed. The method sends a read command to a memory, sends a strobe clock signal after the read command is sent and before the DQS signal is received from the memory, wherein the strobe clock signal comprises a duration equal to a duration of the DQS signal, gates the DQS signal based on the strobe clock signal to generate a positively gated strobe signal for indicating a rising edge of the DQS signal, wherein the gating is performed during a pre-amble of the DQS signal and generates a negatively gated strobe signal based on the positively gated strobe signal for indicating a falling edge of the DQS signal.