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公开(公告)号：US20170162150A1
公开(公告)日：2017-06-08
申请号：US14786071
申请日：2015-09-21
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Juncheng XIAO , Shangcao CAO , Yao YAN , Ronglei DAI
IPC: G09G3/36
CPC classification number: G09G3/3677 , G02F1/133 , G09G3/36 , G09G3/3696 , G09G2300/0408 , G09G2300/0871 , G09G2310/0202 , G09G2310/08
Abstract: A liquid crystal display device and a gate driving circuit are disclosed. The gate driving circuit includes multiple-stage gate driving units and a control chip. Each stage gate driving unit includes a first pulling control unit, a first pulling unit, a second pulling control unit, a second pulling unit, a first control unit, a second control unit and a third control unit. The control chip is used for pulling a first clock signal and a first voltage reference signal to a first voltage level. Accordingly, the scanning lines driven by the gate driving circuit are all turned on in order to stably realize an All-Gate-On function.
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公开(公告)号：US20170154594A1
公开(公告)日：2017-06-01
申请号：US14785907
申请日：2015-09-21
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Juncheng XIAO , Ronglei DAI , Yao YAN , Shangcao CAO
IPC: G09G3/36
CPC classification number: G09G3/3677 , G02F1/13454 , G09G3/3696 , G09G2300/0408 , G09G2300/0426 , G09G2300/0871 , G09G2310/08
Abstract: A liquid crystal display device and a gate driving circuit are disclosed. The gate driving circuit includes multiple-stage gate driving units and a control chip. Each stage gate driving unit includes a first pulling control unit, a first pulling unit, a second pulling control unit, a second pulling unit, a first reset unit, a second reset unit. The control chip is used for pulling a first clock signal and a first voltage reference signal to a first voltage level. Accordingly, the scanning lines driven by the gate driving circuit are all turned on in order to stably realize an All-Gate-On function.
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公开(公告)号：US20170193944A1
公开(公告)日：2017-07-06
申请号：US14900684
申请日：2015-10-21
Applicant: Shenzhen China Star OptoelectronicsTechnology Co. Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Juncheng XIAO , Ronglei DAI , Shangcao CAO , Yao YAN
IPC: G09G3/36
CPC classification number: G09G3/3677 , G02F1/136286 , G02F1/1368 , G02F2203/64 , G09G2300/0408 , G09G2310/0245 , G09G2310/0286 , G09G2310/08 , G09G2320/0214 , G09G2330/026 , G11C19/28
Abstract: The disclosure provides a GOA circuit, a driving method thereof and a liquid crystal display device. The GOA circuit comprises a plurality of GOA units connected in cascade, wherein the N-stage GOA unit comprises a N-stage stage circuit, a N-stage Q point control circuit, a N-stage P point circuit, a N-stage output circuit and a switch circuit. The switch circuit is connected to the N-stage scan line for sending a turn-on signal to the N-stage scan line before the liquid crystal display device displays an image such that the thin-film transistor in the pixel connected to the N-stage scan line turns on. The disclosure may turn on the gate of each pixel when the display device is waken from the black screen to prevent the electricity leakage when the display device is wakened from the black screen, and may also increase the stability of the circuit.
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公开(公告)号：US20170162148A1
公开(公告)日：2017-06-08
申请号：US14888426
申请日：2015-09-29
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Juncheng XIAO , Ronglei DAI , Yao YAN , Shangcao CAO
IPC: G09G3/36 , G02F1/1362
CPC classification number: G09G3/3674 , G02F1/1362 , G09G3/20 , G09G3/3648 , G09G2300/0408 , G09G2300/0434 , G09G2310/0202 , G09G2310/0218 , G09G2310/0267 , G09G2310/0286 , G11C19/287
Abstract: The invention discloses a GOA circuit, a display device and a drive method of a GOA circuit, the GOA circuit is set to be GOA units including a plurality of levels, a N leveled GOA unit is applied to charge a N leveled scanning line of a display region of the display device, the N leveled scanning line is connected to a first gate all on signal and a second gate all on signal, which can guarantee scanning lines corresponding to all the GOA units are being charged under control of the first gate all on signal and the second gate all on signal. The invention can carry out an all gate on function according to the method above.
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公开(公告)号：US20160358564A1
公开(公告)日：2016-12-08
申请号：US14777748
申请日：2015-07-17
Inventor： Juncheng XIAO , Mang ZHAO , Yao YAN
IPC: G09G3/36
CPC classification number: G09G3/20 , G09G2300/0408 , G09G2310/0267
Abstract: A scan driving circuit is provided for driving scan lines which are connected in series, including a pull-down controlling module, a pull-down module, a reset-controlling module, a resetting module, a downward-transmitting module, a first bootstrap capacitor, a constant low voltage level source, and a constant high voltage level source. The entire structure of the scan driving circuit is simple, and energy consumption is reduced.
Abstract translation: 提供扫描驱动电路，用于驱动串联连接的扫描线，包括下拉控制模块，下拉模块，复位控制模块，复位模块，向下传输模块，第一自举电容器 ，恒定的低电压电平源和恒定的高电压电平源。 扫描驱动电路的整体结构简单，能耗降低。
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Patent Agency Ranking
公开(公告)号：US20190011744A1
公开(公告)日：2019-01-10
申请号：US16127767
申请日：2018-09-11
Inventor： Yao YAN , Shangcao CAO
IPC: G02F1/1368 , H01L27/12
Abstract: The array substrate, the liquid crystal display panel and the liquid crystal display device of the present disclosure are designed to form the MIS storage capacitor by the P—Si semiconductor layer, the first metal layer and the insulating layer between above or the P—Si semiconductor layer, the second metal layer and the dielectric spacer layer between above, when one side of the first metal layer or the second metal layer receiving the negative gray voltage, the P—Si in the P—Si semiconductor layer will gather to form the hole, when receiving the positive gray voltage, will form the depletion layer on the upper layer of the P—Si to reduce the capacity of the MIS storage capacitor, thereby reducing the difference of the capacitance when the MIS storage capacitor in the positive and negative gray voltage, improving the flicker phenomena and ensuring the display effect.
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公开(公告)号：US20190004352A1
公开(公告)日：2019-01-03
申请号：US16126078
申请日：2018-09-10
Inventor： Yao YAN , Shangcao CAO
IPC: G02F1/1368 , H01L27/12
Abstract: The array substrate, the liquid crystal display panel and the liquid crystal display device of the present disclosure are designed to from the MIS storage capacitor by the P-Si semiconductor layer, the first metal layer and the insulating layer between above or the P-Si semiconductor layer, the second metal layer and the dielectric spacer layer between above, when one side of the first metal layer or the second metal layer receiving the negative gray voltage, the P-Si in the P-Si semiconductor layer will gather to form the hole, when receiving the positive gray voltage, will form the depletion layer on the upper layer of the P-Si to reduce the capacity of the MIS storage capacitor, thereby reducing the difference of the capacitance when the MIS storage capacitor in the positive and negative gray voltage, improving the flicker phenomena and ensuring the display effect.
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公开(公告)号：US20170256224A1
公开(公告)日：2017-09-07
申请号：US14915222
申请日：2016-01-05
Inventor： Juncheng XIAO , Shangcao CAO , Ronglei DAI , Yao YAN
IPC: G09G3/36
CPC classification number: G09G3/3677 , G06F3/0416 , G09G2300/0408 , G09G2310/0251 , G09G2310/0283 , G09G2310/0286 , G09G2310/08
Abstract: A GOA driving circuit, a TFT display panel and a display device are disclosed. The GOA driving circuit includes: an input module configured for outputting first control signals in accordance with the received display scanning signals and the touch scanning signals; an output module configured for outputting the first output control signals in accordance with the first control signals and the first clock signals; a pull-down module configured for outputting pull-down signals in accordance with the first control signals, the second control signals and the low level signals; and a pull-down maintaining module configure for outputting the second output control signals in accordance with the pull-down signals, the high level signals, and the first clock signals. The DC source is adopted to charge/discharge Qn to keep Qn at a reasonable level, and the transfer capability is enhanced. In addition, the forward scanning and the backward scanning may be implemented.
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公开(公告)号：US20170169784A1
公开(公告)日：2017-06-15
申请号：US14889423
申请日：2015-10-21
Applicant: Shenzhen China Star Optoelectronics Technology Co. Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Juncheng XIAO , Shangcao CAO , Ronglei DAI , Yao YAN
CPC classification number: G09G3/3677 , G09G2300/0408 , G09G2300/0426 , G09G2310/0251 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G11C19/28 , H01L27/124
Abstract: A GOA circuit, a display device, and a driving method of GOA circuit are disclosed. A N-th level GOA unit is configured for charging the N-th level horizontal scanning line (G(N)) within a display area of the display device. The N-th level horizontal scanning line (G(N)) connects to GAS. In response to the GAS, the horizontal scanning lines corresponding to all of the GOA units are in a charging state. In this way, the horizontal scanning lines at each level are connected to the GAS, such that when the GAS are valid, the corresponding horizontal scanning line at each level are in the charging state of in an on-state so as to realize the All Gate On function.
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公开(公告)号：US20190011743A1
公开(公告)日：2019-01-10
申请号：US16127704
申请日：2018-09-11
Inventor： Yao YAN , Shangcao CAO
IPC: G02F1/1368 , H01L27/12
Abstract: The array substrate, the liquid crystal display panel and the liquid crystal display device of the present disclosure are designed to form the MIS storage capacitor by the P—Si semiconductor layer, the first metal layer and the insulating layer between above or the P—Si semiconductor layer, the second metal layer and the dielectric spacer layer between above, when one side of the first metal layer or the second metal layer receiving the negative gray voltage, the P—Si in the P—Si semiconductor layer will gather to form the hole, when receiving the positive gray voltage, will form the depletion layer on the upper layer of the P—Si to reduce the capacity of the MIS storage capacitor, thereby reducing the difference of the capacitance when the MIS storage capacitor in the positive and negative gray voltage, improving the flicker phenomena and ensuring the display effect.
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