ARRAY SUBSTRATE, DISPLAY PANEL AND MOBILE TERMINAL

    公开(公告)号:US20190265565A1

    公开(公告)日:2019-08-29

    申请号:US16110197

    申请日:2018-08-23

    Abstract: The present invention relates to a display panel technology field. An array substrate comprises a first metal layer, a buffer layer, a semiconductor layer, an insulating layer, a scanning metal layer, an inter layer dielectric, and a second metal layer that are sequentially stacked on a glass substrate along a first direction, and a first pixel set and a second pixel set that are arranged alternately along a second direction; and a first conductive path sequentially connecting the first pixel set and a second conductive path sequentially connecting the second pixel set. The first conductive path and the second conductive path change lines alternately in the first metal layer and the second metal layer, such that the first pixel set and the second pixel set are sequentially connected in series. With the array substrate of the present invention, the metal layer for changing line can be eliminated.18

    FAN-OUT WIRE STRUCTURE, DISPLAY PANEL, AND DISPLAY DEVICE

    公开(公告)号:US20210408059A1

    公开(公告)日:2021-12-30

    申请号:US17042136

    申请日:2020-07-23

    Inventor: Zhihao CAO Wei TANG

    Abstract: A fan-out wire structure, a display panel, and a display device are provided. The fan-out wire structure includes a first wiring layer, a second wiring layer, and a plurality of fan-out wires. The fan-out wires include a plurality of first fan-out wires and a plurality of second fan-out wires. The first fan-out wires are disposed in the first wiring layer. The fan-out wires are disposed in the second wiring layer. Each of the first fan-out wires is provided with a first impedance unit. Each of the second fan-out wires is provided with a second impedance unit.

    Array Substrate, Display Panel, and Display Device

    公开(公告)号:US20210167092A1

    公开(公告)日:2021-06-03

    申请号:US16649715

    申请日:2019-12-12

    Inventor: Zhihao CAO

    Abstract: An array substrate, a display panel, and a display device are provided. The array substrate includes a wiring region and a thin film transistor (TFT) device functional region. The wiring region includes a gate electrode layer, a dielectric layer disposed on the gate electrode layer, and a data wire layer disposed on the dielectric layer. A plurality of via holes are defined on the dielectric layer. The data wire layer is connected to the gate electrode layer through the plurality of via holes. A data wire formed from the data wire layer and a gate wire formed from the gate wire electrode layer constitute a parallel connection structure at positions of the plurality of via holes.

    DISPLAY PANEL
    5.
    发明申请

    公开(公告)号:US20230112905A1

    公开(公告)日:2023-04-13

    申请号:US17048775

    申请日:2020-09-10

    Abstract: A display panel and a manufacturing method thereof are disclosed. The display panel includes a plurality of scan lines parallel to one another, a plurality of data lines parallel to one another, a common electrode, and a plurality of connection lines. The scan lines and the data lines are disposed in different layers and perpendicular to each other. A loop of a second metal layer is disposed in a non-display region in the layer in which the data lines are disposed. A plurality of connection lines are disposed to be parallel to the data lines. A plurality of protrusion structures are disposed on the scan lines at intervals along a first direction.

    ARRAY SUBSTRATE AND DISPLAY PANEL

    公开(公告)号:US20210225894A1

    公开(公告)日:2021-07-22

    申请号:US16306589

    申请日:2018-08-07

    Inventor: Zhihao CAO

    Abstract: An array substrate and a display panel are provided. The array substrate includes a first region and a second region. The first region corresponds to a display region of the display panel. The second region corresponds a non-display region of the display panel. The second region includes a substrate and an electrically conductive line formed on the substrate. The second region further includes at least one metal pattern formed between the substrate and the electrically conductive line.

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