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公开(公告)号：US11545104B2
公开(公告)日：2023-01-03
申请号：US16966034
申请日：2020-04-03
Inventor： Mang Zhao
Abstract: A gate driver on array (GOA) device and a display panel are proposed. In the present application, by adding a twenty-first transistor and a first control clock terminal electrically connected to the twenty-first transistor in a forward-reverse scan module to control potentials of a first node and a third node, a leakage of the first node during operation can be reduced, thereby improving reliability of the GOA device.
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公开(公告)号：US10650767B2
公开(公告)日：2020-05-12
申请号：US15735924
申请日：2017-10-21
Inventor： Mang Zhao
IPC: G09G3/36
Abstract: The present disclosure provides a scan-driving circuit and a display device. The scan-driving circuit includes a plurality of series-connecting scan-driving units including an input circuit generating a pull-up control signal and a pull-down control signal; a latch circuit pulling up or pulling down a pull-up control signal point; a processing circuit generating a current scan-driving signal, a cache circuit driving an output of a current scan-driving signal, and a reset circuit clearing the pull-up control signal point. Therefore, it improves driving flexibility and reduces driving power consumption of the display device, and is beneficial to narrow bezel design.
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公开(公告)号：US10235913B2
公开(公告)日：2019-03-19
申请号：US15111765
申请日：2016-06-12
IPC: G02F1/13 , G01R31/26 , G09G3/00 , G02F1/1368 , G02F1/1362
Abstract: A testing circuit includes at least one sub-circuit. The sub-circuit includes a first input end, at least one second input end, at least one third input end, and at least one driving output end. The first switch unit includes controllable switches. The second switch unit includes sub-units and first inverters. The sub-unit includes transmission gates. The control end of the controllable switch connects to the second input end, the first end connects to the first input end, and the second end connects to the input end of the transmission gate. The first control end of the transmission gate connects to the third input end and the input end of the first inverter, the second control end connects to the output end of the first inverter, the output end connects to the driving output end.
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公开(公告)号：US10078992B2
公开(公告)日：2018-09-18
申请号：US14783095
申请日：2015-08-10
Inventor： Juncheng Xiao , Mang Zhao , Yong Tian
CPC classification number: G09G3/3674 , G09G2310/0286 , G09G2320/0223 , G09G2320/041 , G09G2330/021 , G11C19/28
Abstract: A scan driving circuit is disclosed for executing a driving operation for cascaded scan lines and includes a pull-down control module, a pull-down module, a reset control module, a reset module, a down-stream module, a first bootstrap capacitor, a constant low-level voltage source utilized, and a constant high-level voltage source. The whole structure of the disclosed scan driving circuit is simple, and power consumption is low.
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公开(公告)号：US10068542B2
公开(公告)日：2018-09-04
申请号：US14916261
申请日：2016-02-24
Inventor： Mang Zhao
IPC: G09G3/36 , G02F1/1362 , H01L27/12 , G11C19/28
Abstract: A GOA circuit includes GOA circuit units. A holding module is substituted for a capacitor in each GOA circuit unit. A second transistor in the holding module is turned on when a scanning signal does not produce a pulse so that voltage imposed in a first control node is held by a first transistor and a third transistor. Because the transistors form a passage between the first control node and a first constant voltage, the voltage imposed on the first control node does not vary due to electricity leakage. Because a second capacitor is coupled with the first control node, the pulse of the scanning signal output by the GOA circuit unit reaches to an ideal high voltage level. The GOA circuit unit can resolve the problem of easy leakage of electricity. When the scanning signals are output by the GOA circuit unit, the stability is highly ensured.
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Patent Agency Ranking
公开(公告)号：US09972269B2
公开(公告)日：2018-05-15
申请号：US15802865
申请日：2017-11-03
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Juncheng Xiao , Mang Zhao
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G2300/0408 , G09G2310/0251 , G09G2310/0283 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G09G2330/04
Abstract: A GOA circuit and a liquid crystal device (LCD) are disclosed. The GOA circuit includes a plurality of GOA units and a control module. Each of the cascaded GOA units is configured for charging corresponding horizontal scanning lines within a display area when being driven by a first level clock, a second level clock, a first control clock, and a second control clock. After the horizontal scanning lines are fully charged by the GOA circuit, the control module is configured for resetting the gate driving signals to be at the first level, i.e., the invalid level, via the turn-on pulse signals and the negative-voltage constant-voltage source.
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公开(公告)号：US09934745B2
公开(公告)日：2018-04-03
申请号：US14917568
申请日：2016-01-29
Inventor： Caiqin Chen , Mang Zhao
IPC: G09G3/36 , G06F3/041 , G02F1/1345 , G11C19/28
CPC classification number: G09G3/3677 , G02F1/13338 , G02F1/13454 , G06F3/0412 , G06F3/0416 , G09G3/36 , G09G3/3659 , G09G2300/0408 , G09G2310/0283 , G09G2310/0286 , G09G2310/0289 , G09G2310/0291 , G09G2310/08 , G11C19/28
Abstract: The present invention provides a GOA circuit applied for the In Cell type touch display panel. The third transmission gate (TG3) comprising the second P-type thin film transistor (T2) and the third N-type thin film transistor (T3), the first P-type thin film transistor (T1) and the fourth N-type thin film transistor (T4) are added in the output buffer module (600), and the touch control signal (TCK) and the inverted touch control signal (XTCK) are introduced to control the working status of the output buffer module (600). Thus, in the touch scan stage, the third transmission gate (TG3) is deactivated, and the first, the fourth thin film transistors (T1, T4) are activated, and the gate scan driving signal output end (Gate(N)) is floating, and similarly jumps between high, low voltage levels along with that the touch scan driving signal jumps between high, low voltage levels.
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公开(公告)号：US09898990B2
公开(公告)日：2018-02-20
申请号：US15022199
申请日：2016-02-22
Inventor： Mang Zhao
IPC: G09G3/36 , H03K17/687 , G02F1/1345
CPC classification number: G09G3/3677 , G02F1/1345 , G02F1/13454 , G09G3/36 , G09G2300/0408 , G09G2300/0426 , G09G2300/0819 , G09G2310/0286 , G09G2320/0219 , H03K17/6871
Abstract: A gate driving circuit is disclosed. The output circuit is connected with the input circuit and the pulling circuit at a first node, responding to scanning driving signal of previous stage to set the pulling circuit in a first status, using a first reference voltage level to set the first node at a first voltage, and held. The output circuit outputs scanning driving signal of current stage according to a first clock signal. The stabilizing circuit is connected with the pulling circuit at a second node, using the first reference voltage level to set the second node at the first voltage, and held. The pulling control circuit responds to a second clock signal to set the pulling circuit in a second status, using a second reference voltage level to pull voltages of the first and second nodes and to hold the voltages. Accordingly, a current leakage can be reduced.
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公开(公告)号：US09830876B2
公开(公告)日：2017-11-28
申请号：US14786167
申请日：2015-10-10
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Mang Zhao
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G3/3696 , G09G2300/0408 , G09G2300/0871 , G09G2310/0289 , G09G2310/0291 , G09G2310/08
Abstract: The present invention provides a CMOS GOA circuit. The latch module (3) comprises a NOR gate (Y), and the two input ends of the NOR gate (Y) are respectively inputted with the inverted stage transfer signal (XQ(N)) and the global signal (Gas). When the global signal (Gas) is high voltage level, all the scan driving signals (G(N)) of the respective stages are controlled to be raised up to high voltage levels at the same time, and meanwhile, the NOR gate (Y) is controlled to pull down voltage levels of the stage transfer signals (Q(N)) of the respective stages to clear and reset the stage transfer signals (Q(N)) of the respective stages. In comparison with prior art, an independent reset module is not required. The additional components, wirings, and reset signal are eliminated to reduce the rear of the GOA circuit, and simplify the complexity of the signal, which is beneficial to the design of narrow frame panel; besides, by locating the storage capacitors (7) to store the low voltage level of the stage transfer signal (Q(N)) as all the scan driving signals (G(N)) of the respective stages are raised up to high voltage levels at the same time to promote the stability of the GOA circuit.
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公开(公告)号：US20170337860A1
公开(公告)日：2017-11-23
申请号：US15238709
申请日：2016-08-16
Inventor： Shijuan Yi , Mang Zhao
IPC: G09G3/00 , G09G3/36 , G02F1/1345 , G02F1/1362
CPC classification number: G09G3/006 , G02F1/13452 , G02F1/13454 , G02F2001/136254 , G09G3/3648 , G09G2300/0426 , G09G2300/0819 , G09G2310/0297 , G09G2310/08 , G09G2330/12
Abstract: The present invention provides a liquid crystal display panel. The array test circuit (200) comprises a test control unit including a N type thin film transistor and a P type thin film transistor, wherein one thin film transistor is employed to be the output thin film transistor, and the other thin film transistor is employed to be the voltage stabilization thin film transistor. When the liquid crystal display panel is in the normal display state, the test control signal (ATEN) controls the output thin film transistor to be deactivated and controls the voltage stabilization thin film transistor to be activated so that the voltage difference of the gate and the source of the output thin film transistor is zero. Thus, the leakages on the data lines in the active display area (100) are consistent.
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