公开(公告)号：US20240103595A1

公开(公告)日：2024-03-28

申请号：US18534911

申请日：2023-12-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mustafa Ulvi Erdogan ,  Suzanne Mary Vining ,  Bharath Kumar Singareddy ,  Douglas Edward Wente

IPC: G06F1/3215 ,  G06F1/3234 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F1/3215 ,  G06F1/3253 ,  G06F13/385 ,  G06F13/4282 ,  G06F2213/0042

Abstract: High-speed data communication devices, e.g., repeaters, interfacing between a host and a peripheral operate such that high-speed components except for a host-side squelch detector are set or maintained in a deactivated state during an idle period of a micro frame. In an example, a start of a micro frame is detected on a data bus during a first time period. In a second time period after the first time period, the high-speed communication device determines whether at least one data packet is contained in the micro frame. When it is determined during the second time period that no data packet is contained in the micro frame, active components, except a squelch detector, are controlled to be inactive during a third time period after the second time period.

公开(公告)号：US11874718B2

公开(公告)日：2024-01-16

申请号：US17330027

申请日：2021-05-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mustafa Ulvi Erdogan ,  Suzanne Mary Vining ,  Bharath Kumar Singareddy ,  Douglas Edward Wente

IPC: G06F1/3215 ,  G06F13/42 ,  G06F13/38 ,  G06F1/3234

CPC classification number: G06F1/3215 ,  G06F1/3253 ,  G06F13/385 ,  G06F13/4282 ,  G06F2213/0042

Abstract: High-speed data communication devices, e.g., repeaters, interfacing between a host and a peripheral operate such that high-speed components except for a host-side squelch detector are set or maintained in a deactivated state during an idle period of a micro frame. In an example, a start of a micro frame is detected on a data bus during a first time period. In a second time period after the first time period, the high-speed communication device determines whether at least one data packet is contained in the micro frame. When it is determined during the second time period that no data packet is contained in the micro frame, active components, except a squelch detector, are controlled to be inactive during a third time period after the second time period.

公开(公告)号：US20230022405A1

公开(公告)日：2023-01-26

申请号：US17374319

申请日：2021-07-13

Applicant: Texas Instruments Incorporated

Inventor： Anant Shankar Kamath ,  Kanteti Amar ,  Bharath Kumar Singareddy ,  Rakesh Hariharan

IPC: H03K19/00

Abstract: Methods, apparatus, systems, and articles of manufacture corresponding to a low area and high speed termination detection circuit with voltage clamping are disclosed. An example apparatus includes a transistor including a first control terminal, first current terminal and a second current terminal, the second current terminal adapted to be coupled to a load. The apparatus further includes a logic gate including an input coupled to the first current terminal. The apparatus further includes a current source including a second control terminal, a third current terminal coupled to a voltage rail and a fourth current terminal coupled to the first current terminal and the input of the logic gate.

公开(公告)号：US20210250026A1

公开(公告)日：2021-08-12

申请号：US17174119

申请日：2021-02-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Win Naing Maung ,  Bharath Kumar Singareddy ,  Soumi Paul ,  Mayank Garg ,  Suzanne Mary Vining

IPC: H03K19/0185 ,  H04L7/00

Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.

公开(公告)号：US12235705B2

公开(公告)日：2025-02-25

申请号：US18534911

申请日：2023-12-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mustafa Ulvi Erdogan ,  Suzanne Mary Vining ,  Bharath Kumar Singareddy ,  Douglas Edward Wente

IPC: G06F1/3215 ,  G06F1/3234 ,  G06F13/38 ,  G06F13/42

Abstract: High-speed data communication devices, e.g., repeaters, interfacing between a host and a peripheral operate such that high-speed components except for a host-side squelch detector are set or maintained in a deactivated state during an idle period of a micro frame. In an example, a start of a micro frame is detected on a data bus during a first time period. In a second time period after the first time period, the high-speed communication device determines whether at least one data packet is contained in the micro frame. When it is determined during the second time period that no data packet is contained in the micro frame, active components, except a squelch detector, are controlled to be inactive during a third time period after the second time period.

公开(公告)号：US20220206556A1

公开(公告)日：2022-06-30

申请号：US17330027

申请日：2021-05-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mustafa Ulvi Erdogan ,  Suzanne Mary Vining ,  Bharath Kumar Singareddy ,  Douglas Edward Wente

IPC: G06F1/3215 ,  G06F13/42 ,  G06F1/3234 ,  G06F13/38

Abstract: High-speed data communication devices, e.g., repeaters, interfacing between a host and a peripheral operate such that high-speed components except for a host-side squelch detector are set or maintained in a deactivated state during an idle period of a micro frame. In an example, a start of a micro frame is detected on a data bus during a first time period. In a second time period after the first time period, the high-speed communication device determines whether at least one data packet is contained in the micro frame. When it is determined during the second time period that no data packet is contained in the micro frame, active components, except a squelch detector, are controlled to be inactive during a third time period after the second time period.

公开(公告)号：US20220224335A1

公开(公告)日：2022-07-14

申请号：US17700045

申请日：2022-03-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Win Naing Maung ,  Bharath Kumar Singareddy ,  Soumi Paul ,  Mayank Garg ,  Suzanne Mary Vining

IPC: H03K19/0185 ,  H04L7/00 ,  H04B3/36 ,  G06F13/42 ,  H04L25/02

Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.

公开(公告)号：US20250165050A1

公开(公告)日：2025-05-22

申请号：US19033728

申请日：2025-01-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mustafa Ulvi Erdogan ,  Suzanne Mary Vining ,  Bharath Kumar Singareddy ,  Douglas Edward Wente

IPC: G06F1/3215 ,  G06F1/3234 ,  G06F13/38 ,  G06F13/42

Abstract: High-speed data communication devices, e.g., repeaters, interfacing between a host and a peripheral operate such that high-speed components except for a host-side squelch detector are set or maintained in a deactivated state during an idle period of a micro frame. In an example, a start of a micro frame is detected on a data bus during a first time period. In a second time period after the first time period, the high-speed communication device determines whether at least one data packet is contained in the micro frame. When it is determined during the second time period that no data packet is contained in the micro frame, active components, except a squelch detector, are controlled to be inactive during a third time period after the second time period.

公开(公告)号：US20240396554A1

公开(公告)日：2024-11-28

申请号：US18792708

申请日：2024-08-02

Applicant: Texas Instruments Incorporated

Inventor： Win Naing Maung ,  Bharath Kumar Singareddy ,  Soumi Paul ,  Mayank Garg ,  Suzanne Mary Vining

IPC: H03K19/0185 ,  G06F13/42 ,  H04B3/36 ,  H04L7/00 ,  H04L25/02

Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.

公开(公告)号：US12088293B2

公开(公告)日：2024-09-10

申请号：US17700045

申请日：2022-03-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Win Naing Maung ,  Bharath Kumar Singareddy ,  Soumi Paul ,  Mayank Garg ,  Suzanne Mary Vining

IPC: H03K19/0185 ,  G06F13/42 ,  H04B3/36 ,  H04L7/00 ,  H04L25/02

CPC classification number: H03K19/018521 ,  G06F13/4282 ,  H04B3/36 ,  H04L7/0041 ,  H04L25/0272

Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.