公开(公告)号：US20230160953A1

公开(公告)日：2023-05-25

申请号：US17832488

申请日：2022-06-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han WANG ,  Yu-Ting LIN ,  Charlis LIN ,  Coach LIU ,  Wei-Cheng LIU

IPC: G01R31/28 ,  H01L21/768 ,  H01L23/528

CPC classification number: G01R31/2884 ,  H01L21/76898 ,  H01L23/5283 ,  H01L27/088

Abstract: An integrated circuit (IC) chip package and a method of fabricating the same are disclosed. The IC chip package includes a device layer on a first surface of a substrate, a first interconnect structure on the device layer, and a second interconnect structure on the second surface of the substrate. The first interconnect structure includes a fault detection line in a first metal line layer and configured to emit an electrical or an optical signal that is indicative of a presence or an absence of a defect in the device layer, a metal-free region on the fault detection line, and a metal line adjacent to the fault detection line in the first metal line layer. The fault detection line is electrically connected to the device layer.