公开(公告)号：US11907631B2

公开(公告)日：2024-02-20

申请号：US17480574

申请日：2021-09-21

Applicant: Synopsys, Inc.

Inventor： Fahim Rahim ,  Paras Mal Jain ,  Rajarshi Mukherjee ,  Deep Shah ,  Satrajit Pal ,  Dipit Ranjan Senapati ,  Abhishek Kumar

IPC: G06F30/3312 ,  G06F30/31 ,  G06F119/12

CPC classification number: G06F30/3312 ,  G06F30/31 ,  G06F2119/12

Abstract: Reset Domain Crossing (RDC) detection and simulation is provided via identifying a plurality of RDCs between flip-flops of a sequence of flip-flops leading to an observation point in a circuit design; classifying each RDC of the plurality of RDCs as one of observable at the observation point or not observable at the observation point based on a reset order applied to the sequence of flip-flops; and outputting a list of the plurality of RDCs classified as observable at the observation point.