公开(公告)号：US10289773B2

公开(公告)日：2019-05-14

申请号：US15633542

申请日：2017-06-26

Applicant: Synopsys, Inc.

Inventor： Deep Shah ,  Namit Gupta ,  Mohamed Shaker Sarwary

IPC: G06F17/50

Abstract: Information from a circuit design's unified power format (UPF) description is utilized to automate the management of reset domain crossings (RDCs). The UPF description is utilized to identify signals that generate both RDC and power domain crossings (PDCs), thereby allowing a circuit designer to efficiently utilize a common (shared) isolation circuit that functions to manage both the RDC (i.e., during reset functions) and the PDC (i.e., during power management functions). A modified UPF description is introduced that facilitates automated management of RDC issues by treating the reset domains as pseudo-power domains, and utilizing UPF analysis and verification tools to automatically generate both shared and non-shared resources for both RDC and PDC issues.

公开(公告)号：US20160342727A1

公开(公告)日：2016-11-24

申请号：US14716422

申请日：2015-05-19

Applicant: Synopsys, Inc.

Inventor： Mohamed Shaker Sarwary ,  Paras Mal Jain ,  Anshu Malani

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5031 ,  G06F2217/84

Abstract: In a method of checking an integrated circuit design prior to running a simulation, a shoot-through RTL Checker reads RTL design files, uses a simulator delta cycle definitions to compute clock delta delays, and helps to correct and report any conditions that are expected will cause the simulation to generate incorrect results, in particular shoot-through conditions at circuit memory elements such as source and destination flip-flops or registers.

Abstract translation: 在运行仿真之前检查集成电路设计的方法中，直通RTL​​检查器读取RTL设计文件，使用模拟器增量循环定义来计算时钟延迟延迟，并帮助纠正和报告任何预期的条件 导致模拟产生不正确的结果，特别是在诸如源和目标触发器或寄存器的电路存储器元件的直通条件。

公开(公告)号：US20160300009A1

公开(公告)日：2016-10-13

申请号：US14794549

申请日：2015-07-08

Applicant: Synopsys, Inc.

Inventor： Mohamed Shaker Sarwary ,  Hans-Jorg Peter ,  Barsneya Chakrabarti ,  Fahim Rahim ,  Mohammad Homayoun Movahed-Ezazi

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/504 ,  G06F17/5045

Abstract: A system and method use reactive initialization to facilitate formal verification of an electronic logic design. The system verifies that a part of the logic design correctly transitions through a sequence of states by automatically assigning an initial state value. The system interacts with a correction-unit to provide meaningful feedback of verification failures, making it possible for the correction-unit to correct the failures or add new constraints that allow the verification to complete. Assigning an initial state simplifies the verification of the validity of the remaining states in the sequence, thus making it more likely to reach a conclusive result and consuming less computing resources.

Abstract translation: 系统和方法使用反应初始化来促进电子逻辑设计的形式验证。 系统通过自动分配初始状态值来验证逻辑设计的一部分通过一系列状态正确地转变。 系统与校正单元进行交互以提供验证失败的有意义的反馈，使校正单元有可能纠正故障或添加允许验证完成的新约束。 分配初始状态简化了序列中剩余状态的有效性的验证，从而使其更有可能达到确定的结果并消耗较少的计算资源。

公开(公告)号：US20190034571A1

公开(公告)日：2019-01-31

申请号：US16047976

申请日：2018-07-27

Applicant: Synopsys, Inc.

Inventor： Mohamed Shaker Sarwary ,  Hans-Joerg Peter ,  Guillaume Plassan ,  Barsneya Chakrabarti ,  Mohammad Homayoun Movahed-Ezazi

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F2217/62 ,  G06F2217/84

Abstract: Formal verification techniques are used to extract valid clock modes from a hardware description of the clock network. In one aspect, the clock network includes primary clocks and configuration signals as inputs, and also includes derived clocks within the clock network. The derived clocks are configurable for different clock modes according to the values of the configuration signals. A parametric liveness property checking is applied to the derived clocks, where the configuration signals are parameters for the parametric liveness property checking. The parametric liveness property checking infers which values of the configuration signals result in valid clock modes for the derived clocks.

公开(公告)号：US20180004876A1

公开(公告)日：2018-01-04

申请号：US15633542

申请日：2017-06-26

Applicant: Synopsys, Inc.

Inventor： Deep Shah ,  Namit Gupta ,  Mohamed Shaker Sarwary

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F2217/62

Abstract: Information from a circuit design's unified power format (UPF) description is utilized to automate the management of reset domain crossings (RDCs). The UPF description is utilized to identify signals that generate both RDC and power domain crossings (PDCs), thereby allowing a circuit designer to efficiently utilize a common (shared) isolation circuit that functions to manage both the RDC (i.e., during reset functions) and the PDC (i.e., during power management functions). A modified UPF description is introduced that facilitates automated management of RDC issues by treating the reset domains as pseudo-power domains, and utilizing UPF analysis and verification tools to automatically generate both shared and non-shared resources for both RDC and PDC issues.

公开(公告)号：US10387605B2

公开(公告)日：2019-08-20

申请号：US14807676

申请日：2015-07-23

Applicant: Synopsys, Inc.

Inventor： Maher Mneimneh ,  Scott Cotton ,  Mohamed Shaker Sarwary ,  Fahim Rahim ,  Sudeep Mondal ,  Paras Mal Jain

IPC: G06F17/50

Abstract: A system and method for managing and composing verification engines and simultaneously applying such compositions to verify properties with design constraints allocates computing resources to verification engines based upon properties to be checked and optionally a user-specified budget. The verification engines are run in order to verify a received register transfer level (RTL) design description of a circuit according to user-specified assertions and constraints received by the system. The particular verification engines to be run are selected from a database of such engines and a run order is designated in sequential, parallel and distributed flows.

公开(公告)号：US09721058B2

公开(公告)日：2017-08-01

申请号：US14794549

申请日：2015-07-08

Applicant: Synopsys, Inc.

Inventor： Mohamed Shaker Sarwary ,  Hans-Jorg Peter ,  Barsneya Chakrabarti ,  Fahim Rahim ,  Mohammad Homayoun Movahed-Ezazi

IPC: G06F17/00 ,  G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/504 ,  G06F17/5045

Abstract: A system and method use reactive initialization to facilitate formal verification of an electronic logic design. The system verifies that a part of the logic design correctly transitions through a sequence of states by automatically assigning an initial state value. The system interacts with a correction-unit to provide meaningful feedback of verification failures, making it possible for the correction-unit to correct the failures or add new constraints that allow the verification to complete. Assigning an initial state simplifies the verification of the validity of the remaining states in the sequence, thus making it more likely to reach a conclusive result and consuming less computing resources.

公开(公告)号：US09721057B2

公开(公告)日：2017-08-01

申请号：US14790318

申请日：2015-07-02

Applicant: Synopsys, Inc.

Inventor： Malay Ganai ,  Mohamed Shaker Sarwary ,  Maher Mneimneh ,  Paras Mal Jain ,  Mohammad Homayoun Movahed-Ezazi ,  Pronay Kumar Biswas ,  Nishant Gupta

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/62

Abstract: A system and method for netlist clock domain crossing verification leverages RTL clock domain crossing (CDC) verification data and results. The netlist clock domain crossing verification system (NCDC) migrates RTL-level constraints and waivers to the netlist design so that the user does not have to re-enter them. The NCDC checks the netlist and generates a report that compares RTL-level CDC checking results to the netlist-level CDC checking results to make it easy to see new issues. The NCDC receives and stores netlist corrections from user input or automatically corrects certain CDC violations, in the netlist.

公开(公告)号：US10599800B2

公开(公告)日：2020-03-24

申请号：US16047976

申请日：2018-07-27

Applicant: Synopsys, Inc.

Inventor： Mohamed Shaker Sarwary ,  Hans-Joerg Peter ,  Guillaume Plassan ,  Barsneya Chakrabarti ,  Mohammad Homayoun Movahed-Ezazi

IPC: G06F17/50

Abstract: Formal verification techniques are used to extract valid clock modes from a hardware description of the clock network. In one aspect, the clock network includes primary clocks and configuration signals as inputs, and also includes derived clocks within the clock network. The derived clocks are configurable for different clock modes according to the values of the configuration signals. A parametric liveness property checking is applied to the derived clocks, where the configuration signals are parameters for the parametric liveness property checking. The parametric liveness property checking infers which values of the configuration signals result in valid clock modes for the derived clocks.

公开(公告)号：US20170024508A1

公开(公告)日：2017-01-26

申请号：US14807676

申请日：2015-07-23

Applicant: Synopsys, Inc

Inventor： Maher Mneimneh ,  Scott Cotton ,  Mohamed Shaker Sarwary ,  Fahim Rahim ,  Sudeep Mondal ,  Paras Mal Jain

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/504

Abstract: A system and method for managing and composing verification engines and simultaneously applying such compositions to verify properties with design constraints allocates computing resources to verification engines based upon properties to be checked and optionally a user-specified budget. The verification engines are run in order to verify a received register transfer level (RTL) design description of a circuit according to user-specified assertions and constraints received by the system. The particular verification engines to be run are selected from a database of such engines and a run order is designated in sequential, parallel and distributed flows.

Abstract translation: 用于管理和组合验证引擎并同时应用这样的组合以用设计约束验证属性的系统和方法基于要检查的属性和可选地用户指定的预算将计算资源分配给验证引擎。 运行验证引擎，以便根据系统接收的用户指定的断言和约束验证电路的接收到的寄存器传输级（RTL）设计描述。 从这样的引擎的数据库中选择要运行的特定验证引擎，并且在顺序，并行和分布式流中指定运行顺序。