公开(公告)号：US20220238672A1

公开(公告)日：2022-07-28

申请号：US17578981

申请日：2022-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Taein KIM ,  Youngtek OH ,  Suhyeong LEE

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/51 ,  H01L27/11582

Abstract: A vertical NAND flash memory device and a method of manufacturing the same are provided. The vertical NAND flash memory device includes a charge trap layer arranged on an inner wall of a channel hole vertically formed on a substrate. The charge trap layer includes nanostructures distributed in a base. The nanostructures may include a material having a trap density of about 1×1019 cm−3 to about 10×1019 cm−3, and the base may include a material having a conduction band offset (CBO) of about 0.5 eV to about 3.5 eV with respect to the material included in the nanostructures.

公开(公告)号：US20220320135A1

公开(公告)日：2022-10-06

申请号：US17537984

申请日：2021-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngtek OH ,  Hyeyoung KWON ,  Taein KIM ,  Gukhyon YON ,  Minhyun LEE

IPC: H01L27/11582

Abstract: A nonvolatile memory device includes a channel layer, a plurality of gate electrodes and a plurality of separation layers spaced apart from the channel layer and alternately arranged, a charge trap layer between the gate electrodes in the channel layer, and a charge blocking layer between the charge trap layer and the gate electrode.

公开(公告)号：US20220319602A1

公开(公告)日：2022-10-06

申请号：US17708362

申请日：2022-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Taein KIM ,  Youngtek OH ,  Hyeonjin SHIN ,  Changseok LEE

IPC: G11C16/04 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11578

Abstract: Provided is a vertical nonvolatile memory device in which a thickness of one memory cell is reduced to reduce an entire thickness of a memory cell string and increase the number of stacked memory cells. The nonvolatile memory device includes a plurality of memory cell strings. Each of the memory cell strings may include a plurality of insulating spacers each extending in a first direction, a plurality of gate electrodes each extending in the first direction and alternately arranged with the plurality of insulating spacers in a second direction perpendicular to the first direction, and a plurality of contacts respectively arranged to contact a side surface of the plurality of gate electrodes respectively corresponding to the plurality of contacts.