公开(公告)号：US20190131417A1

公开(公告)日：2019-05-02

申请号：US15958061

申请日：2018-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Se Ki HONG ,  Ju Youn KIM ,  Jin-Wook KIM ,  Tae Eung YOON ,  Tae Won HA ,  Jung Hoon SEO ,  Seul Gi YUN

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/28

Abstract: A semiconductor device includes a substrate having first and second active regions with a field insulating layer therebetween that contacts the first and second active regions, and a gate electrode on the substrate and traversing the first active region, the second active region, and the field insulating layer. The gate electrode includes a first portion over the first active region, a second portion over the second active region, and a third portion in contact with the first and second portions. The gate electrode includes an upper gate electrode having first through third thicknesses in the first through third portions, respectively, where the third thickness is greater than the first thickness, and smaller than the second thickness.

公开(公告)号：US20140106535A1

公开(公告)日：2014-04-17

申请号：US14134008

申请日：2013-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyu LEE ,  Kiseok SUH ,  Tae Eung YOON

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1691 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1641

Abstract: A memory device includes a lower interconnection in a semiconductor substrate, the lower interconnection being made of a material different from the semiconductor substrate, a selection element on the lower interconnection, and a memory element on the selection element.

Abstract translation: 存储器件包括半导体衬底中的下互连，下互连由不同于半导体衬底的材料制成，下互连上的选择元件以及选择元件上的存储元件。