公开(公告)号：US20230292491A1

公开(公告)日：2023-09-14

申请号：US18090043

申请日：2022-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungwook Park ,  Sangmin Kang ,  Yoongoo Kang ,  Changwoo Seo ,  Suyoun Song ,  Dain Lee

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/34 ,  H10B12/482 ,  H10B12/0335

Abstract: A semiconductor device may include contact plug structures on a substrate, and an insulation structure filling a space between the contact plug structures to insulate the contact plug structures from each other. The contact plug structures may be spaced apart from each other in a first direction. The insulation structure may include a first insulation pattern and a second insulation pattern. The second insulation pattern may include an insulation material having an etch selectivity with respect to silicon oxide. The first insulation pattern may contact a portion of sidewalls of the second insulation pattern and a portion of sidewalls of the contact plug structure. The first insulation pattern may include a material having a band gap higher than a band gap of the second insulation pattern.

公开(公告)号：US20250142812A1

公开(公告)日：2025-05-01

申请号：US18896219

申请日：2024-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suyoun Song ,  Jamin Koo ,  Beomseo Kim ,  Jonghyeok Kim ,  Daeyoung Moon ,  Changwoo Seo ,  Wonseok Yoo ,  Chunhyung Chung

IPC: H10B12/00 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including a first active region, a bit line on the substrate to cross the first active region, a bit line contact between the bit line and the first active region and in a bit line contact hole extending into the substrate, a bit line contact spacer on a sidewall of the bit line contact within the bit line contact hole, a bit line spacer on a sidewall of the bit line, an anti-oxidation layer between the sidewall of the bit line and the bit line spacer and between the sidewall of the bit line contact and the bit line spacer, and a buried contact in a buried contact hole, passing through the bit line contact spacer, and contacting the first active region, in which the anti-oxidation layer includes a silicon-containing material including SiOx, where 0

公开(公告)号：US12230498B2

公开(公告)日：2025-02-18

申请号：US17222195

申请日：2021-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dain Lee ,  Yoongoo Kang ,  Wonseok Yoo ,  Jinwon Ma ,  Kyungwook Park ,  Changwoo Seo ,  Suyoun Song

IPC: H01L21/02 ,  C23C16/34 ,  C23C16/36 ,  C23C16/455

Abstract: A semiconductor device manufacturing method includes loading a semiconductor substrate into a chamber, the semiconductor substrate including a silicon oxide film, depositing a seed layer on the silicon oxide film by supplying a first silicon source material, supplying a purge gas on the seed layer, depositing a protective layer on the seed layer by repeating a first cycle, the first cycle including supplying a base source material layer and subsequently supplying the first silicon source material, and depositing a silicon nitride film on the protective layer by repeating a second cycle, the second cycle including supplying a second silicon source material and subsequently supplying a nitrogen source material.

公开(公告)号：US20250081429A1

公开(公告)日：2025-03-06

申请号：US18664753

申请日：2024-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youmin Ban ,  Daeyoung Moon ,  Changwoo Seo ,  Suyoun Song ,  Hyungjun Hwang

IPC: H10B12/00

Abstract: A semiconductor device includes a substrate, an active region defined by a device isolation layer within the substrate, a word line extending in a first horizontal direction within the substrate, a bit line extending on the substrate in a second horizontal direction intersecting with the first horizontal direction and including a metal-based conductive pattern, a first spacer on a sidewall of the metal-based conductive pattern, a second spacer on the first spacer, a direct contact in a direct contact hole exposing the active region and electrically connecting the bit line to the active region, and a buried spacer on a lower sidewall of the direct contact within the direct contact hole, wherein the second spacer contacts a sidewall of the direct contact on the sidewall of the direct contact.

公开(公告)号：US20240306375A1

公开(公告)日：2024-09-12

申请号：US18444390

申请日：2024-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suyoun Song ,  Yoongoo Kang ,  Kyungwook Park ,  Youmin Ban ,  Changwoo Seo ,  Hyunchul Shim

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/02

Abstract: An integrated circuit device includes a substrate having a plurality of active regions, a bit line extending in a horizontal direction on the substrate, an insulating capping pattern formed on the bit line and extending along the bit line, a direct contact disposed in a direct contact hole formed on the substrate and connected between a first active region selected from among the plurality of active regions and the bit line, and a spacer structure contacting a sidewall of the direct contact and a sidewall of the bit line The spacer structure includes a first spacer layer extending in a vertical direction on the sidewall of the direct contact and the sidewall of the bit line, and a second spacer layer covering at least a portion of the first spacer layer and extending in the vertical direction.