公开(公告)号：US20250072106A1

公开(公告)日：2025-02-27

申请号：US18435305

申请日：2024-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jisoo PARK ,  Byungju KANG ,  Jaehyoung LIM ,  Kwanyoung CHUN ,  Subin CHOI

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A three-dimensional semiconductor device may include a back-side metal layer, a lower channel pattern on the back-side metal layer, first and second lower source/drain patterns, which are spaced apart from each other in a first direction with the lower channel pattern interposed therebetween, the first lower source/drain pattern being connected to the lower channel pattern, an upper channel pattern on the lower channel pattern, a first upper source/drain pattern on the first lower source/drain pattern, the first upper source/drain pattern being connected to the upper channel pattern, a second upper source/drain pattern on the second lower source/drain pattern, and a wide via electrically connecting the first upper source/drain pattern to the second lower source/drain pattern. The wide via may include first and second via portions having first and second top surfaces, and here, the second top surface may be located at a level lower than the first top surface.

公开(公告)号：US20240120393A1

公开(公告)日：2024-04-11

申请号：US18334849

申请日：2023-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jisoo PARK ,  Myung Il KANG ,  Ji Wook KWON ,  Jung Han LEE ,  Subin CHOI

IPC: H01L29/417 ,  H01L23/48 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L23/481 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate, a first sheet pattern on the substrate, a gate electrode on the substrate and surrounding the first sheet pattern, a first source/drain pattern and a second source/drain pattern respectively connected to a first end and a second end of the first sheet pattern, a contact blocking pattern on a lower side of the second source/drain pattern, a first source/drain contact extending in a first direction and connected to the first source/drain pattern, and a second source/drain contact connected to the second source/drain pattern and extending in the first direction to contact an upper surface of the contact blocking pattern. A depth from an upper surface of the gate electrode to a lowermost portion of the first source/drain contact may be greater than a depth from the upper surface of the gate electrode to the upper surface of the contact blocking pattern.