公开(公告)号：US20160054933A1

公开(公告)日：2016-02-25

申请号：US14561204

申请日：2014-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Siamack HAGHIGHI ,  Robert BRENNAN

IPC: G06F3/06 ,  G06F12/08 ,  G06F12/06

CPC classification number: G06F3/0611 ,  G06F3/064 ,  G06F3/0649 ,  G06F3/0658 ,  G06F3/0685 ,  G06F3/0688 ,  G06F12/0638 ,  G06F2212/205

Abstract: According to one general aspect, an apparatus may include a processor, a heterogeneous memory system, and a memory interconnect. The processor may be configured to perform a data access on data stored in a memory system. The heterogeneous memory system may include a plurality of types of storage mediums. Each type of storage medium may be based upon a respective memory technology and may be associated with one or more performance characteristics. The heterogeneous memory system may include both volatile and non-volatile storage mediums. The memory interconnect may be configured to route the data access from the processor to at least one of the storage mediums based, at least in part, upon the one or more performance characteristic associated with the respective memory technologies of the storage media.

Abstract translation: 根据一个一般方面，设备可以包括处理器，异构存储器系统和存储器互连。 处理器可以被配置为对存储在存储器系统中的数据执行数据访问。 异构存储器系统可以包括多种类型的存储介质。 每种类型的存储介质可以基于相应的存储器技术，并且可以与一个或多个性能特性相关联。 异构存储器系统可以包括易失性存储介质和非易失性存储介质。 至少部分地基于与存储介质的相应存储器技术相关联的一个或多个性能特征，存储器互连可被配置为将数据访问从处理器路由到至少一个存储介质。

公开(公告)号：US20170109101A1

公开(公告)日：2017-04-20

申请号：US14970008

申请日：2015-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Craig HANSON ,  Michael BEKERMAN ,  Siamack HAGHIGHI ,  Chihjen CHANG

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0616 ,  G06F3/0652 ,  G06F3/0685 ,  G06F3/0688

Abstract: A memory module includes a solid-state drive (SSD) and a memory controller. The memory controller receives information from a host memory controller via a synchronous memory channel and determines to initiate background tasks of the SSD based on memory commands and a state of the memory module. According to one embodiment, the synchronous memory channel is a DRAM memory channel, and the SSD includes a flash memory. The background tasks of the SSD such as garbage collection, wear leveling, and erase block preparation are initiated during an idle state of the memory module.

公开(公告)号：US20170017571A1

公开(公告)日：2017-01-19

申请号：US14959298

申请日：2015-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changho CHOI ,  Derrick TSENG ,  Siamack HAGHIGHI

IPC: G06F12/02 ,  G06F12/10 ,  G06F17/30 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/0608 ,  G06F3/0641 ,  G06F3/0652 ,  G06F3/0679 ,  G06F16/2365 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/1056 ,  G06F2212/2022 ,  G06F2212/7201 ,  G06F2212/7205

Abstract: A storage device for deduplicating data includes a memory that stores machine instructions and a controller coupled to the memory to execute the machine instructions in order to compare a data pattern associated with a write request to stored data. If the data pattern matches the stored data, the controller further executes the machine instructions to increment a counter associated with the data pattern and map a source storage address corresponding to the data pattern to a physical storage address associated with the storage device.

Abstract translation: 用于重复数据删除数据的存储设备包括存储机器指令的存储器和耦合到存储器的控制器以执行机器指令，以便将与写入请求相关联的数据模式与存储的数据进行比较。 如果数据模式与存储的数据匹配，则控制器进一步执行机器指令以增加与数据模式相关联的计数器，并将与数据模式对应的源存储地址映射到与存储设备相关联的物理存储地址。

公开(公告)号：US20210311637A1

公开(公告)日：2021-10-07

申请号：US17347550

申请日：2021-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Siamack HAGHIGHI ,  Robert BRENNAN

IPC: G06F3/06 ,  G06F12/06

Abstract: According to one general aspect, an apparatus may include a processor, a heterogeneous memory system, and a memory interconnect. The processor may be configured to perform a data access on data stored in a memory system. The heterogeneous memory system may include a plurality of types of storage mediums. Each type of storage medium may be based upon a respective memory technology and may be associated with one or more performance characteristics. The heterogeneous memory system may include both volatile and non-volatile storage mediums. The memory interconnect may be configured to route the data access from the processor to at least one of the storage mediums based, at least in part, upon the one or more performance characteristic associated with the respective memory technologies of the storage media.

公开(公告)号：US20160100027A1

公开(公告)日：2016-04-07

申请号：US14601228

申请日：2015-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Siamack HAGHIGHI

IPC: H04L29/08

CPC classification number: H04L67/1097 ,  H04L67/1095 ,  H04L69/14

Abstract: Inventive aspects include one or more local servers each including a local universal access logic section, one or more remote servers each including a remote universal access logic section, and a coherency node to provide coherent access to first data that is stored on the one or more local servers to the one or more remote servers, and to provide coherent access to second data that is stored on the one or more remote servers to the one or more local servers. Embodiments of the inventive concept herein can use hardware and/or software mechanism to unify direct and remote attached devices via command, data, status, and completion memory queues. Applications and operating systems can be presented with a uniform access interface for sharing data and resources across multiple disparately situated servers and nodes.

Abstract translation: 发明方面包括一个或多个本地服务器，每个本地服务器包括本地通用访问逻辑部分，每个包括远程通用访问逻辑部分的一个或多个远程服务器和一致性节点，以提供对存储在一个或多个 本地服务器到一个或多个远程服务器，并且将一个或多个远程服务器上存储的第二数据提供给一个或多个本地服务器的一致访问。 本发明构思的实施例可以使用硬件和/或软件机制来通过命令，数据，状态和完成存储器队列来统一直接和远程连接的设备。 应用程序和操作系统可以呈现统一的访问接口，用于跨多个不同位置的服务器和节点共享数据和资源。