公开(公告)号：US20250169058A1

公开(公告)日：2025-05-22

申请号：US18761823

申请日：2024-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongjae BYEON ,  Si Nyeon KIM ,  Wonsok LEE ,  Juho LEE

IPC: H10B12/00

Abstract: A semiconductor device may include a bit line extending in a first direction on a substrate, a first insulating pattern extending in a second direction on the bit line, a channel pattern contacting a sidewall of the first insulating pattern and the bit line and including an oxide semiconductor material, a word line extending in the second direction and spaced apart from the channel pattern, a gate insulating pattern between the channel pattern and the word line, a second insulating pattern on the word line and the gate insulating pattern, and a landing pad electrically connected to the channel pattern. A second portion of the channel pattern between the gate insulating pattern and the bit line may be thicker than a first portion of the channel pattern, which may be between the gate insulating pattern and the first insulating pattern. The second direction may intersect the first direction.

公开(公告)号：US20250063726A1

公开(公告)日：2025-02-20

申请号：US18738410

申请日：2024-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Si Nyeon KIM ,  Seong Jae BYEON

IPC: H10B12/00

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a first bit line extending in a first direction on a substrate, a word line on the first bit line, and extending in a second direction intersecting the first direction, a first channel pattern between the first bit line and the word line, and extending along a first side wall of the word line and a first contact pattern on the first channel pattern, wherein in a cross-sectional view taken along the first channel pattern in the second direction, the first contact pattern includes a connecting part on the first channel pattern, and a protruding part which is connected to the connecting part, and extends along a side wall of the first channel pattern.

公开(公告)号：US20240222123A1

公开(公告)日：2024-07-04

申请号：US18356322

申请日：2023-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kang In KIM ,  Si Nyeon KIM ,  Jiho PARK ,  Youngwoo SON ,  Ji-Eun LEE ,  Young-Seung CHO

IPC: H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/0337 ,  H01L21/0332 ,  H01L21/3086 ,  H01L21/31144 ,  H01L29/4236 ,  H01L29/6653 ,  H01L29/6656

Abstract: A method of fabricating a semiconductor device may include forming an active pattern on a substrate, sequentially forming on the substrate a base mask, a first mask layer, a first capping layer, a second mask layer, a second capping layer, a third mask layer, a third capping layer, a fourth mask layer, and a fourth capping layer, forming first spacers, forming second spacers, forming third spacers, and using the third spacers as a mask to pattern the first mask layer and the first capping layer. Forming the third spacers may include forming a spacer layer to completely fill a space between the sidewalls of patterns of the patterned second mask layer.