公开(公告)号：US11342283B2

公开(公告)日：2022-05-24

申请号：US16810091

申请日：2020-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungwook Kim ,  Ayoung Kim ,  Seongwon Jeong ,  Sangsu Ha

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/00

Abstract: Provided a package substrate including an insulation substrate, a conductive layer provided in the insulation substrate, upper pads provided on an upper surface of the insulation substrate and electrically connected to the conductive layer, lower pads provided on a lower surface of the insulation substrate and electrically connected to the conductive layer, and at least one trench provided at a portion of the insulation substrate adjacent to at least one of the upper pads and configured to block stress, which is generated by an expansion of the insulation substrate, from spreading to the at least one of the upper pads.

公开(公告)号：US11640950B2

公开(公告)日：2023-05-02

申请号：US17210695

申请日：2021-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungwook Kim ,  Ahram Kang ,  Seongwon Jeong

IPC: H01L23/00 ,  H01L23/538

Abstract: A semiconductor chip includes; an intermetal dielectric (IMD) layer on a substrate, an uppermost insulation layer on the IMD layer, the uppermost insulation layer having a dielectric constant different from a dielectric constant of the IMD layer, a metal wiring in the IMD layer, the metal wiring including a via contact and a metal pattern, a metal pad in the uppermost insulation layer, the metal pad being electrically connected to the metal wiring, and a bump pad on the metal pad. An interface portion between the IMD layer and the uppermost insulation layer is disposed at a height of a portion between an upper surface and a lower surface of an uppermost metal pattern in the IMD layer.

公开(公告)号：US11784139B2

公开(公告)日：2023-10-10

申请号：US17750903

申请日：2022-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungwook Kim ,  Ayoung Kim ,  Seongwon Jeong ,  Sangsu Ha

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/562 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2924/3512

Abstract: Provided a package substrate including an insulation substrate, a conductive layer provided in the insulation substrate, upper pads provided on an upper surface of the insulation substrate and electrically connected to the conductive layer, lower pads provided on a lower surface of the insulation substrate and electrically connected to the conductive layer, and at least one trench provided at a portion of the insulation substrate adjacent to at least one of the upper pads and configured to block stress, which is generated by an expansion of the insulation substrate, from spreading to the at least one of the upper pads.

公开(公告)号：US20230130436A1

公开(公告)日：2023-04-27

申请号：US17743971

申请日：2022-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungwook Kim ,  Ayoung Kim ,  Seongwon Jeong ,  Sangsu Ha

IPC: H01L23/498

Abstract: A semiconductor package includes a package substrate having a first surface and a second surface opposite to the first surface, and including a plurality of bonding pads exposed to the first surface and a plurality of solder bumps respectively disposed on the bonding pads, and at least one semiconductor device arranged on the package substrate. Each of the solder bumps includes a bump body disposed on the bonding pad, a plurality of bonding particles provided inside the bump body to be adjacent to the bonding pad, and a first metal compound layer provided to surround the bonding particles and having a protrusion structure for strengthening adhesion with the bonding pad.