公开(公告)号：US20240038675A1

公开(公告)日：2024-02-01

申请号：US18313491

申请日：2023-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jimin CHOI ,  Joongwon SHIN ,  Sungyun WOO ,  Yeonjin LEE ,  Jongmin LEE ,  Sehyun HWANG

IPC: H01L23/544 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/544 ,  H01L25/0657 ,  H01L25/18 ,  H10B80/00 ,  H01L2225/06513 ,  H01L2225/06582 ,  H01L2225/06593 ,  H01L2223/54426

Abstract: A semiconductor device may include a plurality of chip regions on a substrate, at least one scribe lane surrounding each of the plurality of chip regions on the substrate, a plurality of first align key patterns and a plurality of first test element group patterns included in the plurality of chip regions, and a plurality of second align key patterns and a plurality of second test element group patterns included in the at least one scribe lane.