公开(公告)号：US12175208B2

公开(公告)日：2024-12-24

申请号：US16989391

申请日：2020-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinook Song ,  Daekyeung Kim ,  Junseok Park ,  Joonho Song ,  Sehwan Lee ,  Junwoo Jang ,  Yunkyo Cho

IPC: G06F7/544 ,  G06N3/063

Abstract: An arithmetic apparatus includes a first operand holding circuit configured to output a first operand according to a clock signal, generate an indicator signal based on bit values of high-order bit data including a most significant bit of the first operand, and gate the clock signal based on the indicator signal, the clock signal being applied to a flip-flop latching the high-order bit data of the first operand; a second operand holding circuit configured to output a second operand according to the clock signal; and an arithmetic circuit configured to perform data gating on the high-order bit data of the first operand based on the indicator signal and output an operation result by performing an operation using a modified first operand resulting from the data gating and the second operand.

公开(公告)号：US12099912B2

公开(公告)日：2024-09-24

申请号：US16446610

申请日：2019-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Ali Shafiee Ardestani ,  Joseph H. Hassoun ,  Lei Wang ,  Sehwan Lee ,  JoonHo Song ,  Jun-Woo Jang ,  Yibing Michelle Wang ,  Yuecheng Li

IPC: G06N3/04 ,  G06F9/30 ,  G06F17/15 ,  G06F17/16 ,  G06N3/08 ,  G06T9/00

CPC classification number: G06N3/04 ,  G06F17/153 ,  G06F17/16 ,  G06N3/08 ,  G06T9/002 ,  G06F9/3001

Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.

公开(公告)号：US12073302B2

公开(公告)日：2024-08-27

申请号：US18219904

申请日：2023-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Ali Shafiee Ardestani ,  Joseph H. Hassoun ,  Lei Wang ,  Sehwan Lee ,  JoonHo Song ,  Jun-Woo Jang ,  Yibing Michelle Wang ,  Yuecheng Li

IPC: G06N3/04 ,  G06F9/30 ,  G06F17/15 ,  G06F17/16 ,  G06N3/08 ,  G06T9/00

CPC classification number: G06N3/04 ,  G06F17/153 ,  G06F17/16 ,  G06N3/08 ,  G06T9/002 ,  G06F9/3001

Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.

公开(公告)号：US11875255B2

公开(公告)日：2024-01-16

申请号：US16803342

申请日：2020-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsun Park ,  Yoojin Kim ,  Hyeongseok Yu ,  Sehwan Lee ,  Junwoo Jang

IPC: G06N3/08 ,  G06N3/04

CPC classification number: G06N3/08 ,  G06N3/04

Abstract: A method of processing data in a neural network, includes identifying a sparsity of input data, based on valid information included in the input data in which the input data includes valid values and invalid values, generate rearranged input data, based on a form of the sparsity by rearranging, in the input data, location of at least one of the valid values and the invalid values, and generating, by performing a convolution on the rearranged input data in the neural network, an output.

公开(公告)号：US11853888B2

公开(公告)日：2023-12-26

申请号：US18089696

申请日：2022-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonho Song ,  Namjoon Kim ,  Sehwan Lee ,  Deokjin Joo

IPC: G06N3/08 ,  G06F7/74 ,  G06N20/00

CPC classification number: G06N3/08 ,  G06F7/74 ,  G06N20/00

Abstract: A processor-implemented method of performing convolution operations in a neural network includes generating a plurality of first sub-bit groups and a plurality of second sub-bit groups, respectively from at least one pixel value of an input feature map and at least one predetermined weight, performing a convolution operation on a first pair that includes a first sub-bit group including a most significant bit (MSB) of the at least one pixel value and a second sub-bit group including an MSB of the at least one predetermined weight, based on the plurality of second sub-bit groups, obtaining a maximum value of a sum of results for convolution operations of remaining pairs excepting the first pair, and based on a result of the convolution operation on the first pair and the maximum value, determining whether to perform the convolution operations of the remaining pairs.

公开(公告)号：US11568243B2

公开(公告)日：2023-01-31

申请号：US16704290

申请日：2019-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonho Song ,  Namjoon Kim ,  Sehwan Lee ,  Deokjin Joo

IPC: G06N3/08 ,  G06F7/74 ,  G06N20/00

Abstract: A processor-implemented method of performing convolution operations in a neural network includes generating a plurality of first sub-bit groups and a plurality of second sub-bit groups, respectively from at least one pixel value of an input feature map and at least one predetermined weight, performing a convolution operation on a first pair that includes a first sub-bit group including a most significant bit (MSB) of the at least one pixel value and a second sub-bit group including an MSB of the at least one predetermined weight, based on the plurality of second sub-bit groups, obtaining a maximum value of a sum of results for convolution operations of remaining pairs excepting the first pair, and based on a result of the convolution operation on the first pair and the maximum value, determining whether to perform the convolution operations of the remaining pairs.

公开(公告)号：US20180253636A1

公开(公告)日：2018-09-06

申请号：US15870767

申请日：2018-01-12

Applicant: Samsung Electronics Co., Ltd. ,  Seoul National University R&DB Foundation

Inventor： Sehwan Lee ,  Dongyoung Kim ,  Sungjoo Yoo

IPC: G06N3/02

CPC classification number: G06N3/02 ,  G06N3/0454 ,  G06N3/063

Abstract: A neural network processor and method include a fetch controller configured to receive input feature information, indicating whether each of a plurality of input features of an input feature map includes a non-zero value, and weight information, indicating whether each of a plurality of weights of a weight map includes a non-zero value, and configured to determine input features and weights to be convoluted, from among the plurality of input features and the plurality of weights, based on the input feature information and the weight information. The neural network processor and method also include a data arithmetic circuit configured to convolute the determined weights and input features to generate an output feature map.

公开(公告)号：US12248868B2

公开(公告)日：2025-03-11

申请号：US17376516

申请日：2021-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Woo Jang ,  Jinook Song ,  Sehwan Lee

IPC: G06N3/06 ,  G06N3/04 ,  G06N3/063

Abstract: A neural processing device includes a first memory configured to store universal data, a second memory distinguished from the first memory and having a capacity less than that of the first memory, a bandwidth control path configured to reconfigure a memory bandwidth for memory clients to use one of the first memory and the second memory based on a control signal, and a control logic configured to calculate a target capacity for data of a target client of the memory clients determined based on a layer configuration of an artificial neural network, and generate the control signal to store the data of the target client in the second memory based on a result of comparing the target capacity and the capacity of the second memory.

公开(公告)号：US20240411599A1

公开(公告)日：2024-12-12

申请号：US18225041

申请日：2023-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Zhi-Gang Liu ,  Jun Woo Jang ,  Sehwan Lee ,  Dongkyun Kim

IPC: G06F9/50 ,  G06F9/48

Abstract: An integrated circuit includes: a central processing unit (CPU) core; an accelerator; and an acceleration instruction queue connected to the CPU core and the accelerator. The CPU core is to: fetch and decode one or more instructions from among an instruction sequence in a programmed order; determine an instruction from among the one or more instructions containing an acceleration workload encoded therein; and queue the instruction containing the acceleration workload encoded therein in the acceleration instruction queue.

公开(公告)号：US11915118B2

公开(公告)日：2024-02-27

申请号：US18107210

申请日：2023-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Saptarsi Das ,  Sabitha Kusuma ,  Sehwan Lee ,  Ankur Deshwal ,  Kiran Kolar Chandrasekharan

IPC: G06N3/04 ,  G06F17/16

CPC classification number: G06N3/04 ,  G06F17/16

Abstract: A method and an apparatus for processing layers in a neural network fetch Input Feature Map (IFM) tiles of an IFM tensor and kernel tiles of a kernel tensor, perform a convolutional operation on the IFM tiles and the kernel tiles by exploiting IFM sparsity and kernel sparsity, and generate a plurality of OFM tiles corresponding to the IFM tiles.