公开(公告)号：US20220415772A1

公开(公告)日：2022-12-29

申请号：US17673865

申请日：2022-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanggyoo Jung ,  Seungbin Baek ,  Hyunjung Song ,  Sangmin Yong

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L23/00

Abstract: Provided is a semiconductor package including a first wiring pad on a package substrate; a first wiring connection part on the first wiring pad and including a wiring solder layer; a second wiring pad on the package substrate; a second wiring connection part on the second wiring pad and including a conductor; an interposer substrate on the first wiring connection part and the second wiring connection part, wherein a first substrate connection part and a second substrate connection part respectively electrically connected to the first wiring connection part and the second wiring connection part are arranged on a rear surface of the interposer substrate; and semiconductor chips apart from each other in a two-dimensional manner on the interposer substrate, wherein each of the semiconductor chips is electrically connected to the interposer substrate via a chip connection pillar.

公开(公告)号：US12272628B2

公开(公告)日：2025-04-08

申请号：US17673865

申请日：2022-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanggyoo Jung ,  Seungbin Baek ,  Hyunjung Song ,  Sangmin Yong

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L25/18

Abstract: Provided is a semiconductor package including a first wiring pad on a package substrate; a first wiring connection part on the first wiring pad and including a wiring solder layer; a second wiring pad on the package substrate; a second wiring connection part on the second wiring pad and including a conductor; an interposer substrate on the first wiring connection part and the second wiring connection part, wherein a first substrate connection part and a second substrate connection part respectively electrically connected to the first wiring connection part and the second wiring connection part are arranged on a rear surface of the interposer substrate; and semiconductor chips apart from each other in a two-dimensional manner on the interposer substrate, wherein each of the semiconductor chips is electrically connected to the interposer substrate via a chip connection pillar.

公开(公告)号：US11935867B2

公开(公告)日：2024-03-19

申请号：US17398406

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanggyoo Jung ,  Sungeun Kim ,  Sangmin Yong ,  Hae-Jung Yu

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L23/64

CPC classification number: H01L25/0652 ,  H01L23/5383 ,  H01L23/642 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/3511

Abstract: A semiconductor package comprising a package substrate that extends in a first direction and a second direction perpendicular to the first direction, a plurality of logic dies and a memory stack structure on the package substrate, and an interposer substrate mounted in the package substrate. The memory stack structure vertically overlaps the interposer substrate. Each of the logic dies includes a first part that is horizontally offset from the interposer substrate and a second part that vertically overlaps the interposer substrate. The interposer substrate includes an interlayer dielectric layer and a plurality of wiring lines in the interlayer dielectric layer. The memory stack structure is electrically connected to at least one of the logic dies through the wiring lines of the interposer substrate.

公开(公告)号：US12021032B2

公开(公告)日：2024-06-25

申请号：US18326325

申请日：2023-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yanggyoo Jung ,  Jinhyun Kang ,  Sungeun Kim ,  Sangmin Yong ,  Seungkwan Ryu

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/5383 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0655 ,  H01L24/32 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1517

Abstract: A semiconductor package includes a package substrate. An interposer is disposed on the package substrate. The interposer includes a semiconductor substrate, a wiring layer disposed on an upper surface of the semiconductor substrate and having a plurality of wirings therein, redistribution wiring pads disposed on the wiring layer and electrically connected to the wirings, bonding pads disposed on the redistribution wiring pads, and an insulation layer pattern disposed on the wiring layer and exposing at least a portion of the bonding pad, and first and second semiconductor devices disposed on the interposer. The first and second semiconductor devices are spaced apart from each other and are electrically connected to each other by at least one of the wirings.

公开(公告)号：US11694961B2

公开(公告)日：2023-07-04

申请号：US17208512

申请日：2021-03-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yanggyoo Jung ,  Jinhyun Kang ,  Sungeun Kim ,  Sangmin Yong ,  Seungkwan Ryu

IPC: H01L23/538 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/5383 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0655 ,  H01L24/32 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1517

Abstract: A semiconductor package includes a package substrate. An interposer is disposed on the package substrate. The interposer in a semiconductor substrate, a wiring layer disposed on an upper surface of the semiconductor substrate and having a plurality of wirings therein, redistribution wiring pads disposed on the wiring layer and electrically connected to the wirings, bonding pads disposed on the redistribution wiring pads, and an insulation layer pattern disposed on the wiring layer and exposing at least a portion of the bonding pad, and first and second semiconductor devices disposed on the interposer. The first and second semiconductor devices are spaced apart from each other and are electrically connected to each other by at least one of the wirings.

公开(公告)号：US20210391265A1

公开(公告)日：2021-12-16

申请号：US17208512

申请日：2021-03-22

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Yanggyoo Jung ,  Jinhyun Kang ,  Sungeun Kim ,  Sangmin Yong ,  Seungkwan Ryu

IPC: H01L23/538 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor package includes a package substrate. An interposer is disposed on the package substrate. The interposer in a semiconductor substrate, a wiring layer disposed on an upper surface of the semiconductor substrate and having a plurality of wirings therein, redistribution wiring pads disposed on the wiring layer and electrically connected to the wirings, bonding pads disposed on the redistribution wiring pads, and an insulation layer pattern disposed on the wiring layer and exposing at least a portion of the bonding pad, and first and second semiconductor devices disposed on the interposer. The first and second semiconductor devices are spaced apart from each other and are electrically connected to each other by at least one of the wirings.