公开(公告)号：US11469306B2

公开(公告)日：2022-10-11

申请号：US16995044

申请日：2020-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jee-Sun Lee ,  Dong Soo Woo ,  Nam Ho Jeon

IPC: H01L29/423 ,  H01L27/108

Abstract: A semiconductor device including a substrate having isolation films and active regions that are defined by the isolation films. The active regions extend in a first direction. A first trench is disposed on the substrate. Second trenches are disposed in the active regions. A filling film is disposed in the first trench. First gate patterns are disposed on the filling film in the first trench. Second gate patterns are disposed in the second trenches. The second gate patterns extend in a second direction that is different from the first direction. The filling film includes at least one material selected from a semiconductor material film and a metal.

公开(公告)号：US20180301456A1

公开(公告)日：2018-10-18

申请号：US15821089

申请日：2017-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Hee Cho ,  Jun Soo Kim ,  Hui Jung Kim ,  Tae Yoon An ,  Satoru Yamada ,  Won Sok Lee ,  Nam Ho Jeon ,  Moon Young Jeong ,  Ki Jae Hur ,  Jae Ho Hong

IPC: H01L27/108 ,  H01L27/12

CPC classification number: H01L27/10802 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10844 ,  H01L27/10876 ,  H01L27/1207 ,  H01L29/4236

Abstract: A semiconductor device and a method for fabricating the same are provided. A semiconductor device having a substrate can include a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer. A first trench can be in the upper semiconductor layer having a lowest surface above the buried insulating layer and a first conductive pattern recessed in the first trench. A second trench can be in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer. A second conductive pattern can be in the second trench and a first source/drain region can be in the upper semiconductor layer between the first conductive pattern and the second conductive pattern.

公开(公告)号：US10770463B2

公开(公告)日：2020-09-08

申请号：US16437784

申请日：2019-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Hee Cho ,  Jun Soo Kim ,  Hui Jung Kim ,  Tae Yoon An ,  Satoru Yamada ,  Won Sok Lee ,  Nam Ho Jeon ,  Moon Young Jeong ,  Ki Jae Hur ,  Jae Ho Hong

IPC: H01L27/108 ,  H01L27/12 ,  H01L21/84 ,  H01L29/423 ,  H01L21/768

Abstract: A semiconductor device and a method for fabricating the same are provided. A semiconductor device having a substrate can include a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer. A first trench can be in the upper semiconductor layer having a lowest surface above the buried insulating layer and a first conductive pattern recessed in the first trench. A second trench can be in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer. A second conductive pattern can be in the second trench and a first source/drain region can be in the upper semiconductor layer between the first conductive pattern and the second conductive pattern.

公开(公告)号：US10361205B2

公开(公告)日：2019-07-23

申请号：US15821089

申请日：2017-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Hee Cho ,  Jun Soo Kim ,  Hui Jung Kim ,  Tae Yoon An ,  Satoru Yamada ,  Won Sok Lee ,  Nam Ho Jeon ,  Moon Young Jeong ,  Ki Jae Hur ,  Jae Ho Hong

IPC: H01L27/108 ,  H01L27/12 ,  H01L21/768 ,  H01L29/423

Abstract: A semiconductor device and a method for fabricating the same are provided. A semiconductor device having a substrate can include a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer. A first trench can be in the upper semiconductor layer having a lowest surface above the buried insulating layer and a first conductive pattern recessed in the first trench. A second trench can be in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer. A second conductive pattern can be in the second trench and a first source/drain region can be in the upper semiconductor layer between the first conductive pattern and the second conductive pattern.