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公开(公告)号:US20240429307A1
公开(公告)日:2024-12-26
申请号:US18745976
申请日:2024-06-17
Applicant: Samsung Electronics Co., Ltd.
Inventor: Rebecca PARK , Mehdi SAREMI , Ming HE , Muhammed AHOSAN UL KARIM , Aravindh KUMAR , Harsono SIMKA
IPC: H01L29/66 , H01L29/417 , H01L29/78
Abstract: Provided are systems, methods, and apparatuses for applying stress in transistors. In one or more examples, the systems, devices, and methods include depositing an epitaxial film on a surface between a first sidewall and a second sidewall of the transistor; depositing a dielectric over the epitaxial film and on the surface between the first sidewall and the second sidewall to increase stress in a silicon channel of the transistor; removing a polysilicon fin between the second sidewall and a third sidewall; and depositing a first metal between the second sidewall and the third sidewall based on removing the polysilicon fin.
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公开(公告)号:US20240047456A1
公开(公告)日:2024-02-08
申请号:US17984042
申请日:2022-11-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Ming HE , Mehdi SAREMI , Rebecca PARK , Muhammed AHOSAN UL KARIM , Harsono SIMKA , Sungil PARK , Myungil KANG , Kyungho KIM , Doyoung CHOI , JaeHyun PARK
IPC: H01L27/088 , H01L29/417 , H01L29/06 , H01L29/423 , H01L29/78
CPC classification number: H01L27/088 , H01L29/41725 , H01L29/0607 , H01L29/42392 , H01L29/0673 , H01L29/785
Abstract: Provided is a three-dimensionally stacked field-effect transistor (3DSFET) device which includes: a 1st lower source/drain region and a 2nd lower source/drain region connected to each other through a 1st lower channel structure controlled by a 1st gate structure; and a 1st upper source/drain region and a 2nd upper source/drain regions, respectively above the 1st lower source/drain region and the 2nd lower source/drain region, and connected to each other through a 1st upper channel structure controlled by the 1st gate structure, wherein the 2nd lower source/drain region and the 2nd upper source/drain region form a PN junction therebetween.
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