公开(公告)号：US20180240808A1

公开(公告)日：2018-08-23

申请号：US15714254

申请日：2017-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minyeong SONG ,  Chadong Yeo ,  Jaeduk Lee ,  Jaehoon Jang

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  G11C16/12

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  H01L27/11565 ,  H01L27/1157

Abstract: A three-dimensional (3D) semiconductor memory device includes an electrode structure including a plurality of cell electrodes vertically stacked on a substrate and extending in a first direction, lower and upper string selection electrodes sequentially stacked on the electrode structure, a first vertical structure penetrating the lower and upper string selection electrodes and the electrode structure, a second vertical structure spaced apart from the upper string selection electrode and penetrating the lower string selection electrode and the electrode structure, and a first bit line intersecting the electrode structure and extending in a second direction different from the first direction. The first bit line is connected in common to the first and second vertical structures. The second vertical structure does not extend through the upper string selection electrode.