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    MEMORY DEVICE AND MEMORY SYSTEM
    2.
    发明申请
    MEMORY DEVICE AND MEMORY SYSTEM 有权

    公开(公告)号：US20250060886A1

    公开(公告)日：2025-02-20

    申请号：US18805709

    申请日：2024-08-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ki-Heung Kim ,  ChangSik Yoo ,  Jeongdon Ihm ,  Hyongryol Hwang

    IPC: G06F3/06

    Abstract: A memory device includes at least one bank including at least a first sub-bank and a second sub-bank disposed in a wordline direction. The first sub-bank may include a normal data region connected to a plurality of first wordlines and storing normal data, the second sub-bank may include a metadata region connected to a plurality of second wordlines and storing metadata corresponding to the normal data, the plurality of first wordlines may match the plurality of second wordlines to form a plurality of wordline pairs, and the first sub-bank and the second sub-bank may share a row hammer region storing a number of access times to the plurality of wordline pairs.

    VOLATILE MEMORY DEVICE
    3.
    发明申请
    VOLATILE MEMORY DEVICE 有权

    公开(公告)号：US20240395313A1

    公开(公告)日：2024-11-28

    申请号：US18657523

    申请日：2024-05-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ki-Heung Kim ,  Taeyoung Oh

    IPC: G11C11/408

    Abstract: A memory device includes a bank connected to a plurality of wordlines and a plurality of column select lines (CSLs). Among the plurality of wordlines, every r-th wordline in a column direction may be allocated for metadata where r is a positive integer.

    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF TESTING SEMICONDUCTOR MEMORY DEVICES
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF TESTING SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20200227130A1

    公开(公告)日：2020-07-16

    申请号：US16574808

    申请日：2019-09-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ki-Heung Kim ,  Kyo-Min Sohn ,  Young-Soo Sohn

    IPC: G11C29/38 ,  H01L25/065 ,  G11C11/4076 ,  G11C29/12

    Abstract: An integrated circuit device includes a stack of integrated circuit memory dies having a plurality of through-substrate vias (TSVs) extending therethrough, and a buffer die electrically coupled to the plurality of TSVs. The buffer die includes a test interface circuit, which is configured to: (i) generate a plurality of internal test signals, which are synchronized with a second clock signal having a second frequency, from at least one control code, and from a plurality of external test signals, which are synchronized with a first clock signal having a first frequency less than the second frequency, and (ii) provide the plurality of internal test signals to at least one of the memory dies in said stack during a first test mode. The second frequency may be greater than three (3) times the first frequency.

    MEMORY DEVICE AND MEMORY MODULE INCLUDING THE SAME
    5.
    发明申请
    MEMORY DEVICE AND MEMORY MODULE INCLUDING THE SAME 有权

    公开(公告)号：US20250078906A1

    公开(公告)日：2025-03-06

    申请号：US18818007

    申请日：2024-08-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ki-Heung Kim ,  ChangSik Yoo ,  Jeongdon Ihm ,  Hyongryol Hwang

    IPC: G11C11/408 ,  G11C11/4093 ,  G11C11/4096

    Abstract: A memory device includes a bank array including a plurality of memory cells, a row decoder connected to the bank array through a plurality of wordlines, and a column decoder connected to the bank array through a plurality of column select lines. The bank array may include a first region and a second region different from the first region. First metadata for first normal data stored in the first region is stored in the second region, and second metadata for second normal data stored in the second region is stored in the first region.

    MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    6.
    发明申请
    MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权

    公开(公告)号：US20240404584A1

    公开(公告)日：2024-12-05

    申请号：US18678401

    申请日：2024-05-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ki-Heung Kim ,  Taeyoung Oh ,  Jongcheol Kim ,  Kyung-Ho Lee ,  Hyongryol Hwang

    IPC: G11C11/4096 ,  G11C11/4076 ,  G11C11/4093

    Abstract: An example memory device includes a memory cell array, a row hammer management circuit, and a read-modify-write (RMW) driver. The memory cell array includes a plurality of memory cell rows and stores count data for a number of accesses to each memory cell row. The row hammer management circuit performs an RMW operation that reads out count data corresponding to a target memory cell row among the memory cell rows, updates the read-out count data, and writes the updated count data in the memory cell array. The RMW driver generates control signals to control the RMW operation based on a precharge command. The target memory cell row is precharged after a predetermined time is elapsed from a time point where the precharge command is applied.

    MEMORY DEVICE AND MEMORY SYSTEM
    8.
    发明申请
    MEMORY DEVICE AND MEMORY SYSTEM 有权

    公开(公告)号：US20250061939A1

    公开(公告)日：2025-02-20

    申请号：US18806022

    申请日：2024-08-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ki-Heung Kim ,  ChangSik Yoo ,  Jeongdon Ihm ,  Hyongryol Hwang

    IPC: G11C11/4096 ,  G11C11/408

    Abstract: A memory device includes at least one bank including a first sub-bank and a second sub-bank disposed in a wordline direction. The first sub-bank may store normal data and may be connected to a plurality of first wordlines, the second sub-bank may store metadata corresponding to the normal data and may be connected to a plurality of second wordlines, and metadata for normal data corresponding to each of the first wordlines may be stored in each of second wordlines, respectively corresponding to the first wordlines.

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