公开(公告)号：US11652066B2

公开(公告)日：2023-05-16

申请号：US17466750

申请日：2021-09-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongjoon Oh ,  Sukho Lee ,  Jusuk Kang

IPC: H01L23/552 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/552 ,  H01L23/3157 ,  H01L23/49534 ,  H01L24/09 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/02379

Abstract: A method of manufacturing a semiconductor package includes forming an encapsulant covering at least a portion of each of an inactive surface and side surface of a semiconductor chip, the semiconductor chip having an active surface on which a connection pad is disposed and the inactive surface opposing the active surface; forming a connection structure having a first region and a second region sequentially disposed on the active surface of the semiconductor chip, and the connection structure including a plurality of redistribution layers electrically connected to the connection pad of the semiconductor chip and further including a ground pattern layer; and forming a metal layer disposed on an upper surface of the encapsulant, and extending from the upper surface of the encapsulant to a side surface of the first region of the connection structure.

公开(公告)号：US20200152582A1

公开(公告)日：2020-05-14

申请号：US16592131

申请日：2019-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongjoon Oh ,  Sukho Lee ,  Jusuk Kang

IPC: H01L23/552 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, a first encapsulant covering at least portions of the inactive surface and a side surface of the semiconductor chip, a connection structure having first and second regions disposed sequentially on the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pad of the semiconductor chip and including a ground pattern layer, and a metal layer disposed on the upper surface of the first encapsulant, and extending from the upper surface of the first encapsulant to the side surface of the first region of the connection structure. The first region of the connection structure has a first width, and the second region has a second width, smaller than the first width.

公开(公告)号：US20230361046A1

公开(公告)日：2023-11-09

申请号：US18095642

申请日：2023-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juil Choi ,  Jusuk Kang ,  Hyungjun Park ,  Sanghyuck Oh ,  Hyunju Lee ,  Sangyeol Choi

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H10B80/00

CPC classification number: H01L23/5383 ,  H01L23/49811 ,  H01L23/3128 ,  H01L23/49816 ,  H10B80/00

Abstract: Provided are a semiconductor package having a structure maximizing heat dissipation efficiency and a method of manufacturing the same. The semiconductor package includes a first redistribution substrate, a first semiconductor chip on the first redistribution substrate, a plurality of through posts on the first redistribution substrate, around the first semiconductor chip, and a second redistribution substrate located over the first semiconductor chip and the through posts, wherein a top surface of the first semiconductor chip is in contact with a bottom surface of the second redistribution substrate.

公开(公告)号：US11139251B2

公开(公告)日：2021-10-05

申请号：US16592131

申请日：2019-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongjoon Oh ,  Sukho Lee ,  Jusuk Kang

IPC: H01L23/552 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, a first encapsulant covering at least portions of the inactive surface and a side surface of the semiconductor chip, a connection structure having first and second regions disposed sequentially on the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pad of the semiconductor chip and including a ground pattern layer, and a metal layer disposed on the upper surface of the first encapsulant, and extending from the upper surface of the first encapsulant to the side surface of the first region of the connection structure. The first region of the connection structure has a first width, and the second region has a second width, smaller than the first width.