公开(公告)号：US12216577B2

公开(公告)日：2025-02-04

申请号：US17882159

申请日：2022-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junwoo Lee

IPC: G06F3/06 ,  G06F12/0802

Abstract: A host for managing a storage device is provided. The host includes a storage host interface configured to communicate with the storage device comprising a cache and a non-volatile memory and at least one processor. The at least one processor may be configured to receive information indicating cache loss from the storage device after device reset of the storage device, suspend a data input/output operation for the storage device, transmit a buffer read command to the storage device, and receive cache information related to data remaining in the cache without being stored in the non-volatile memory before the device reset from the storage device in response to the buffer read command.

公开(公告)号：US11901297B2

公开(公告)日：2024-02-13

申请号：US18153028

申请日：2023-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyeok Son ,  Junwoo Lee ,  Sungdong Cho

IPC: H01L23/535 ,  H01L21/768 ,  H10B12/00

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76895 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/09 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482 ,  H10B12/485 ,  H10B12/50

Abstract: A semiconductor memory device includes a substrate including a cell area and a peripheral area, a plurality of capacitors including a plurality of lower electrodes arranged in the cell area, a plurality of capacitor dielectric layers covering the plurality of lower electrodes, and an upper electrode on the plurality of capacitor dielectric layers, an etch stop layer covering the upper electrode, a filling insulation layer covering the etch stop layer and arranged in the cell area and the peripheral area, a plurality of wiring lines on the filling insulation layer, and a first wiring contact plug electrically connecting at least one of the plurality of wiring lines to the upper electrode. The upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers and including a semiconductor material and a second upper electrode layer covering the first upper electrode layer and including a metallic material.

公开(公告)号：US11704072B2

公开(公告)日：2023-07-18

申请号：US17866012

申请日：2022-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonsuk Jung ,  Junwoo Lee ,  Jintae Jang

IPC: G06F3/06 ,  G06F1/28 ,  G06F1/3234 ,  G06F1/3296

CPC classification number: G06F3/0659 ,  G06F1/28 ,  G06F1/3275 ,  G06F1/3296 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0679

Abstract: The various embodiments disclose an electronic device including: a storage including a non-volatile memory having a buffer space and a storage space, a storage device controller, and a storage interface, and a processor. According to various embodiments, the processor may be configured to perform control to determine whether the storage supports a high speed data storage mode using a buffer space of a non-volatile memory of the storage, activate a function of writing data buffered in the buffer space of the non-volatile memory into a storage space of the non-volatile memory based on the storage interface operating in a first state based on the storage supporting the high speed data storage mode, and transition the storage interface of the storage to the first state based on no request to the storage being generated during a predetermined time period based on the storage interface operating in a second state.

公开(公告)号：US11616018B2

公开(公告)日：2023-03-28

申请号：US17398043

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juik Lee ,  Joongwon Shin ,  Jihoon Chang ,  Junghoon Han ,  Junwoo Lee

IPC: H01L23/528 ,  H01L23/532 ,  H01L25/065 ,  H01L25/18 ,  H01L23/522 ,  H01L27/108 ,  H01L23/00 ,  H01L23/48

Abstract: A semiconductor device includes a plurality of middle interconnections and a plurality of middle plugs, which are disposed in an interlayer insulating layer and on a substrate. An upper insulating layer is disposed on the interlayer insulating layer. A first upper plug, a first upper interconnection, a second upper plug, and a second upper interconnection are disposed in the upper insulating layer. Each of the plurality of middle interconnections has a first thickness. The first upper interconnection has a second thickness that is greater than the first thickness. The second upper interconnection has a third thickness that is greater than the first thickness. The third thickness is twice to 100 times the first thickness. The second upper interconnection includes a material different from the second upper plug.

公开(公告)号：US11133253B2

公开(公告)日：2021-09-28

申请号：US16885438

申请日：2020-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juik Lee ,  Joongwon Shin ,  Jihoon Chang ,  Junghoon Han ,  Junwoo Lee

IPC: H01L23/528 ,  H01L23/532 ,  H01L25/065 ,  H01L25/18 ,  H01L23/522 ,  H01L27/108 ,  H01L23/00 ,  H01L23/48

Abstract: A semiconductor device includes a plurality of middle interconnections and a plurality of middle plugs, which are disposed in an interlayer insulating layer and on a substrate. An upper insulating layer is disposed on the interlayer insulating layer. A first upper plug, a first upper interconnection, a second upper plug, and a second upper interconnection are disposed in the upper insulating layer. Each of the plurality of middle interconnections has a first thickness. The first upper interconnection has a second thickness that is greater than the first thickness. The second upper interconnection has a third thickness that is greater than the first thickness. The third thickness is twice to 100 times the first thickness. The second upper interconnection includes a material different from the second upper plug.

公开(公告)号：US12183680B2

公开(公告)日：2024-12-31

申请号：US18191418

申请日：2023-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyeok Son ,  Junwoo Lee ,  Sungdong Cho

IPC: H01L23/535 ,  H01L21/768 ,  H10B12/00

Abstract: A semiconductor memory device includes a substrate including a cell area and a peripheral area, a plurality of capacitors including a plurality of lower electrodes arranged in the cell area, a plurality of capacitor dielectric layers covering the plurality of lower electrodes, and an upper electrode on the plurality of capacitor dielectric layers, an etch stop layer covering the upper electrode, a filling insulation layer covering the etch stop layer and arranged in the cell area and the peripheral area, a plurality of wiring lines on the filling insulation layer, and a first wiring contact plug electrically connecting at least one of the plurality of wiring lines to the upper electrode. The upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers and including a semiconductor material and a second upper electrode layer covering the first upper electrode layer and including a metallic material.

公开(公告)号：US20230238331A1

公开(公告)日：2023-07-27

申请号：US18191418

申请日：2023-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyeok Son ,  Junwoo Lee ,  Sungdong Cho

IPC: H01L23/535 ,  H01L21/768 ,  H10B12/00

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H10B12/485 ,  H01L21/76843 ,  H10B12/34 ,  H10B12/315 ,  H10B12/50 ,  H10B12/482 ,  H01L21/76895 ,  H10B12/0335 ,  H10B12/09 ,  H10B12/053

Abstract: A semiconductor memory device includes a substrate including a cell area and a peripheral area, a plurality of capacitors including a plurality of lower electrodes arranged in the cell area, a plurality of capacitor dielectric layers covering the plurality of lower electrodes, and an upper electrode on the plurality of capacitor dielectric layers, an etch stop layer covering the upper electrode, a filling insulation layer covering the etch stop layer and arranged in the cell area and the peripheral area, a plurality of wiring lines on the filling insulation layer, and a first wiring contact plug electrically connecting at least one of the plurality of wiring lines to the upper electrode. The upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers and including a semiconductor material and a second upper electrode layer covering the first upper electrode layer and including a metallic material.

公开(公告)号：US11569171B2

公开(公告)日：2023-01-31

申请号：US17330795

申请日：2021-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyeok Son ,  Junwoo Lee ,  Sungdong Cho

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/535

Abstract: A semiconductor memory device includes a substrate including a cell area and a peripheral area, a plurality of capacitors including a plurality of lower electrodes arranged in the cell area, a plurality of capacitor dielectric layers covering the plurality of lower electrodes, and an upper electrode on the plurality of capacitor dielectric layers, an etch stop layer covering the upper electrode, a filling insulation layer covering the etch stop layer and arranged in the cell area and the peripheral area, a plurality of wiring lines on the filling insulation layer, and a first wiring contact plug electrically connecting at least one of the plurality of wiring lines to the upper electrode. The upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers and including a semiconductor material and a second upper electrode layer covering the first upper electrode layer and including a metallic material.