公开(公告)号：US11450610B2

公开(公告)日：2022-09-20

申请号：US16876600

申请日：2020-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Hyun ,  Dongug Ko ,  Joohee Park ,  Juhak Song ,  Jongseon Ahn ,  Sungwon Cho

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: A vertical semiconductor device may include may include a substrate, a stacked structure, an insulating interlayer, a buffer pattern and a first contact plug. The stacked structure may include insulation patterns and conductive patterns stacked on each other on the substrate. The conductive patterns may extend in a first direction parallel to an upper surface of the substrate, and edges of the conductive patterns may have a staircase shape. The conductive patterns may include pad patterns defined by exposed upper surfaces of the conductive patterns. The insulating interlayer may cover the stacked structure. The buffer pattern may be on the insulating interlayer. The first contact plug may pass through the buffer pattern and the insulating interlayer. The first contact plug may contact one of the pad patterns. The buffer pattern may reduce defects from forming the first contact plug.

公开(公告)号：US11322515B2

公开(公告)日：2022-05-03

申请号：US16826677

申请日：2020-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juhak Song

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11565 ,  H01L23/522

Abstract: A three-dimensional semiconductor device is disclosed. The device may include first and second stacks separated from each other in a first direction, with each of the stacks including electrodes vertically stacked on a substrate. The device may also include vertical channel structures that penetrate the electrodes and are connected to the substrate, an interlayered insulating layer on top surfaces of the vertical channel structures, and a support pattern located between opposite sidewalls of the first and second stacks, in the interlayered insulating layer. A bottom surface of the support pattern may be positioned at a higher level than a top surface of an uppermost electrode of the electrodes.

公开(公告)号：US20210020657A1

公开(公告)日：2021-01-21

申请号：US16826677

申请日：2020-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juhak Song

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556 ,  H01L23/528 ,  H01L23/522

Abstract: A three-dimensional semiconductor device is disclosed. The device may include first and second stacks separated from each other in a first direction, with each of the stacks including electrodes vertically stacked on a substrate. The device may also include vertical channel structures that penetrate the electrodes and are connected to the substrate, an interlayered insulating layer on top surfaces of the vertical channel structures, and a support pattern located between opposite sidewalls of the first and second stacks, in the interlayered insulating layer. A bottom surface of the support pattern may be positioned at a higher level than a top surface of an uppermost electrode of the electrodes.