公开(公告)号：US20230189524A1

公开(公告)日：2023-06-15

申请号：US17884853

申请日：2022-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Gu KANG ,  Sang Don ZOO ,  Joon Sung KIM ,  Junghwan PARK ,  Seorim MOON ,  Seok Cheon BAEK ,  Cheol RYOU ,  Sun Young LEE ,  Cheol-Min LIM

IPC: H01L27/11582 ,  H01L23/535

CPC classification number: H01L27/11582 ,  H01L23/535

Abstract: A semiconductor memory device may include a substrate including a first and a second block region, and a stacked structure including insulating films and gate electrodes alternately stacked on the substrate. A vertical channel structure, a word line cut structure, and a block cut structure may penetrate the stacked structure. The word line cut structure may extend in a second direction. The block cut structure may extend in a first direction, connect to the word line cut structure, and define the first and second block regions. The block cut structure may include a first portion connected to the word line cut structure and a second portion connected to the first portion. From a planar viewpoint, the first portion may include at least a part not overlapping the second portion in the first direction and at least a region not overlapping the word line cut structure in the first direction.

公开(公告)号：US20230114139A1

公开(公告)日：2023-04-13

申请号：US17900172

申请日：2022-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon SON ,  Joon Sung KIM ,  Suk Kang SUNG ,  Gil Sung LEE ,  Jong-Min LEE

IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11573

Abstract: A semiconductor memory device may include a cell substrate including a cell array region and an extension region, a first mold structure on the cell substrate, a second mold structure on the first mold structure, a channel structure passing through the first and second mold structures on the cell array region, and a cell contact structure passing through the first and second mold structures on the extension region. The first mold structure and the second mold structure respectively include first gate electrodes and second gate electrodes sequentially stacked on the cell array region and stacked in a stepwise manner on the extension region. The cell contact structure includes a lower conductive pattern connected to one of the first gate electrodes, an upper conductive pattern connected to one of the second gate electrodes, and an insulating pattern separating the lower conductive pattern from the upper conductive pattern.