公开(公告)号：US20250151445A1

公开(公告)日：2025-05-08

申请号：US18742302

申请日：2024-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ingyu BAEK ,  Jinmyoung LEE ,  Soonhyung HONG

IPC: H01L27/146

Abstract: An image sensor that includes a first layer and a second layer bonded to the first layer. The first layer includes a first substrate including a first front surface and a first back surface, a floating diffusion region formed in the first substrate, a first pad, and a first conductive line provided between the floating diffusion region and the first pad. The second layer includes a second substrate including a second front surface and a second back surface, pixel transistors formed on the second substrate, a second pad, and a second conductive line provided between one of the pixel transistors and the second pad. The second conductive line passes through the second substrate and is electrically connected to a lower portion of the pixel transistor.

公开(公告)号：US20230223391A1

公开(公告)日：2023-07-13

申请号：US17972180

申请日：2022-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinmyoung LEE ,  Hyungsoon JANG ,  Baekyoung KIM ,  Hyunah ROH ,  Jongsoo BAEK ,  Boyoung LEE

IPC: H01L27/02 ,  G06F30/392

CPC classification number: H01L27/0207 ,  G06F30/392

Abstract: A semiconductor device includes a substrate having first to fourth regions, first to third active regions and a first dummy active region extending on the first to fourth regions, respectively, a first gate structure intersecting the first active region on the first region and including a first gate conductive layer, a second gate structure intersecting the second active region on the second region and including a second gate conductive layer, a third gate structure intersecting the third active region on the third region find including a third gate conductive layer, a first dummy gate structure intersecting the first dummy active region on the fourth region and including a first dummy gate conductive layer, and source/drain regions on the first to third active regions and on both sides of the first to third gate structures.