公开(公告)号：US20240281323A1

公开(公告)日：2024-08-22

申请号：US18469894

申请日：2023-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungkyu Lee ,  Seongmuk Kang ,  Jiho Kim ,  Kijun Lee ,  Kyomin Sohn

IPC: G06F11/10

CPC classification number: G06F11/1044

Abstract: A memory controller including a processor and configured to control a memory module including a plurality of data chips and at least one parity chip includes an error correction code (ECC) engine, the ECC engine including an ECC decoder to correct Q symbols errors in a codeword set read from the memory module, Q is a maximum natural number equal to or less than P and P is a natural number equal to or greater than four. The ECC decoder is configured to generate a syndrome including first through P-th syndrome symbols based on the read codeword set by using a parity check matrix and to perform a first ECC decoding to correct a single symbol error in the read codeword set based on the first syndrome symbol and a selected syndrome symbol corresponding to one of the second through P-th syndrome symbols.

公开(公告)号：US12272867B2

公开(公告)日：2025-04-08

申请号：US17903504

申请日：2022-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiho Kim ,  Seongyong An ,  Sehyun Park

IPC: H01Q1/38 ,  H01Q1/24 ,  H01Q5/25 ,  H04M1/02 ,  H05K1/14

Abstract: A printed board assembly (PBA) is provided. The PBA includes first printed circuit board (PCB), a second PCB disposed parallel to the first PCB and including a conductive area, a first interposer surrounding a space between the first PCB and the second PCB, and a wireless communication circuit, wherein the interposer may include a first partition wall structure configured to provide shielding for at least one electronic component disposed in the PBA, and a second partition wall structure connected to the first partition wall structure and including an dielectric material, the second partition wall structure including a conductive via configured to connect the first PCB and the second PCB, and the wireless communication circuit may transmit and/or receive a signal in a specified frequency band by feeding power to the conductive area of the second PCB through the conductive via.

公开(公告)号：US12218439B2

公开(公告)日：2025-02-04

申请号：US17863996

申请日：2022-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiho Kim ,  Moohyun Roh ,  Gyubok Park ,  Kyungmoon Seol ,  Seongyong An ,  Kyihyun Jang ,  Jaewon Choe

IPC: H01Q5/328 ,  H01Q5/335 ,  H01Q5/50

Abstract: An electronic device is provided. The electronic device includes a housing including a conductive member on which at least one power supply point and ground point are positioned, at least one ground member arranged inside the housing, a first ground path connecting the ground point to the ground member, a second ground path connecting the ground point to the ground member, a printed circuit board (PCB) arranged inside the housing and a processor arranged on the PCB. The processor is configured to supply power to the at least one power supply point so that the conductive member transmits and/or receives a signal of a first frequency band.

公开(公告)号：US11670559B2

公开(公告)日：2023-06-06

申请号：US17206295

申请日：2021-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minjung Choi ,  Jung-Hoon Han ,  Jiho Kim ,  Young-Yong Byun ,  Yeonjin Lee ,  Jihoon Chang

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/528 ,  H01L23/00 ,  H01L23/58 ,  H01L23/29 ,  H01L21/78

CPC classification number: H01L23/3171 ,  H01L23/3192 ,  H01L23/528 ,  H01L21/78 ,  H01L23/291 ,  H01L23/296 ,  H01L23/585 ,  H01L24/05 ,  H01L2224/0219 ,  H01L2224/0221 ,  H01L2224/02181 ,  H01L2224/05541 ,  H01L2224/05553

Abstract: A semiconductor device including a substrate including a chip region and an edge region; integrated circuit elements on the chip region; an interlayer insulating layer covering the integrated circuit elements; an interconnection structure on the interlayer insulating layer and having a side surface on the edge region; a first and second conductive pattern on the interconnection structure, the first and second conductive patterns being electrically connected to the interconnection structure; a first passivation layer covering the first and second conductive patterns and the side surface of the interconnection structure; and a second passivation layer on the first passivation layer, wherein the second passivation layer includes an insulating material different from the first passivation layer, and, between the first and second conductive patterns, the second passivation layer has a bottom surface that is located at a vertical level lower than a top surface of the first conductive pattern.

公开(公告)号：US11316266B2

公开(公告)日：2022-04-26

申请号：US17106778

申请日：2020-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaewon Choe ,  Jiho Kim ,  Moohyun Roh ,  Gyubok Park ,  Kyungmoon Seol ,  Seongyong An ,  Kyihyun Jang

IPC: H01Q1/52 ,  H01Q1/24 ,  H04M1/02

Abstract: An electronic device for minimizing parasitic emission is provided. The electronic device includes a housing including a front cover, a rear cover located on the opposite side of the front cover, and a lateral member surrounding a space between the front cover and the rear cover, the lateral member having a first conductive portion formed on at least a portion thereof, a support member disposed in the space of the housing and including a second conductive portion having therein at least one opening, a display including a conductive sheet that is disposed between the front cover and the support member so as to be visible from an outside through at least a part of the front cover and is disposed to face the support member, and a wireless communication circuit electrically connected to the first conductive portion. The conductive sheet includes a first portion, a second portion disposed adjacent to the first portion, and a coupling that is partly connected between the first portion and the second portion. In case the front cover is viewed from above, the coupling is disposed at a position overlapping the opening.

公开(公告)号：US12255383B2

公开(公告)日：2025-03-18

申请号：US18624631

申请日：2024-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mincheol Seo ,  Donghun Shin ,  Minkyung Lee ,  Jiho Kim ,  Sunghyup Lee ,  Kyihyun Jang ,  Huiwon Cho

IPC: H01Q1/24 ,  H01Q9/04

Abstract: An electronic device is provided. The electronic device includes a housing including a side member, a support member, a display, an antenna module including one or more patch antennas, a printed circuit board (PCB), a wireless communication circuit disposed on the PCB, a first conductive member, a first connector, a second connector, and a protrusion extending from the first end of the first conductive member toward an interior of the housing, and electrically connected to the first conductive member. The antenna module is disposed at locations corresponding to a first opening defined by the first conductive member, the support member, the first connector, and the second connector, and a second opening defined by the first conductive member, the support member, the first connector, and the protrusion, and the wireless communication circuit is electrically connected to the protrusion and the antenna module.

公开(公告)号：US20240385925A1

公开(公告)日：2024-11-21

申请号：US18543737

申请日：2023-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungkyu Lee ,  Seongmuk Kang ,  Daehyun Kim ,  Jiho Kim ,  Kyomin Sohn ,  Kijun Lee ,  Sunghye Cho

IPC: G06F11/10 ,  G06F11/00 ,  G06F11/07

Abstract: A memory system includes a plurality of volatile memory devices and a memory controller. The memory controller includes a plurality of volatile memory devices; and a memory controller configured to control the plurality of volatile memory devices, wherein the memory controller includes: a host interface configured to communicate with a host device based on a Compute eXpress Link (CXL) communication protocol; an error correction level (ECL) manager configured to receive cache line data from the host device through the host interface, and output an error correction code (ECC) control signal indicating one of a first correction level and a second correction level being error correction levels based on cell reliability information and data reliability request information which are associated with the cache line data; and an ECC engine configured to, based on the ECC control signal indicating the first correction level, generate first parity symbols associated with the cache line data, and based on the ECC control signal indicating the second correction level, generate additional parity symbols.

公开(公告)号：US11791184B2

公开(公告)日：2023-10-17

申请号：US17719722

申请日：2022-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiho Kim ,  Minhyeok Kwon ,  Shigenobu Maeda ,  Jooyeok Seo ,  Minuk Lee

IPC: H01L21/67 ,  G05B19/418

CPC classification number: H01L21/67276 ,  G05B19/41865 ,  G05B2219/32291 ,  G05B2219/33034 ,  G05B2219/45031

Abstract: The program code, when executed by a processor, causes the processor to input fabrication data including a plurality of parameters associated with a semiconductor fabricating process to a framework to generate a first class for analyzing the fabrication data, to extract a first parameter targeted for analysis and a second parameter associated with the first parameter from the plurality of parameters and generate a second class for analyzing the first parameter as a sub class of the first class, to modify the first parameter and the second parameter into a data structure having a format appropriate to store in the second class, so as to be stored in the second class, to perform data analysis on the first parameter and the second parameter, to transform the first parameter and the second parameter into corresponding tensor data, and to input the tensor data to the machine learning model.

公开(公告)号：US20250130891A1

公开(公告)日：2025-04-24

申请号：US18657360

申请日：2024-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonghyeog Choi ,  Jiho Kim ,  Changkyu Seol ,  Yuseok Song ,  Daewook Kim

IPC: G06F11/10

Abstract: A memory system includes a semiconductor memory device and a memory controller to control the semiconductor memory device. The semiconductor memory device includes a memory cell array that is divided into a plurality of sub array blocks arranged in a first direction and a second direction. The memory controller includes an error correction code (ECC) engine. The ECC engine, in a write operation, generates a parity data by performing an ECC encoding on a user data including a plurality of sub data units, generates a main data by interleaving the sub data units based on mapping information such that two sub data units to be stored in one row of a target sub array block are included in one symbol. The mapping information indicates a mapping relationship between the plurality of sub data units and rows of the target sub array block storing the plurality of sub data units.

公开(公告)号：US12279388B2

公开(公告)日：2025-04-15

申请号：US17568862

申请日：2022-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiho Kim ,  Kyihyun Jang ,  Seongyong An ,  Sehyun Park ,  Kyungmoon Seol ,  Jaebong Chun

IPC: H05K5/02 ,  H05K5/00 ,  H05K9/00

Abstract: According to an embodiment of the disclosure, an electronic device may include: a housing including a first housing and a second housing configured to be slidable with respect to the first housing, and a flexible display including a first area visible to the outside of the electronic device and a second area configured to extend from the first area such that, based on sliding of the second housing, the second area is moved out of the housing or is moved into an inner space of the housing, wherein the housing comprises a conductive part facing a front surface of the flexible display, and the conductive part is electrically connected to a conductive layer forming a rear surface of the flexible display or is positioned on the rear surface.