公开(公告)号：US20230161937A1

公开(公告)日：2023-05-25

申请号：US17951580

申请日：2022-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Somin Cheon ,  Joonsung Kim ,  Jaewan Song ,  Seunghune Yang ,  Sooyong Lee

IPC: G06F30/3323 ,  G03F7/20

CPC classification number: G06F30/3323 ,  G03F7/70433 ,  G03F7/705 ,  G06F2119/18

Abstract: A mask layout design method capable of quickly and effectively designing a crack-resistant mask layout in a full-chip scale, a mask manufacturing method including the mask layout design method, and a mask layout are provided. The mask layout design method includes designing a full-chip layout with respect to a mask; extracting a representative pattern from the full-chip layout; detecting a stress weak point in the representative pattern; verifying the stress weak point by forming a pattern on a wafer; and changing a design rule with respect to the full-chip layout.