公开(公告)号：US20220238666A1

公开(公告)日：2022-07-28

申请号：US17404078

申请日：2021-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohee KIM ,  Gyeom KIM ,  Jinbum KIM ,  Jaemun KIM ,  Seunghun LEE

IPC: H01L29/417 ,  H01L29/78 ,  H01L27/088

Abstract: An integrated circuit (IC) device includes a fin-type active region extending in a first lateral direction on a substrate, a gate line extending in a second lateral direction on the fin-type active region, an insulating spacer covering a sidewall of the gate line, a source/drain region at a position adjacent to the gate line, a metal silicide film covering a top surface of the source/drain region, and a source/drain contact apart from the gate line with the insulating spacer therebetween in the first lateral direction. The source/drain contact includes a bottom contact segment being in contact with a top surface of the metal silicide film and an upper contact segment integrally connected to the bottom contact segment. A width of the bottom contact segment is greater than a width of at least a portion of the upper contact segment in the first lateral direction.

公开(公告)号：US20230268441A1

公开(公告)日：2023-08-24

申请号：US18307279

申请日：2023-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun KIM ,  Dahye KIM ,  Jinbum KIM ,  Gyeom KIM ,  Dohee KIM ,  Dongwoo KIM ,  Seunghun LEE

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234

CPC classification number: H01L29/785 ,  H01L29/66818 ,  H01L29/41791 ,  H01L29/6681 ,  H01L21/823431 ,  H01L29/045

Abstract: A semiconductor device includes a substrate including a fin-type active region, the fin-type active region extending in a first direction; a plurality of channel layers on the fin-type active region, the plurality of channel layers including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer isolated from direct contact with each other in a direction perpendicular to an upper surface of the substrate; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; a gate insulating film between the plurality of channel layers and the gate electrode; and source/drain regions electrically connected to the plurality of channel layers. In a cross section taken in the second direction, the uppermost channel layer has a width greater than a width of the intermediate channel layer.

公开(公告)号：US20240413246A1

公开(公告)日：2024-12-12

申请号：US18809745

申请日：2024-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun KIM ,  Dahye KIM ,  Jinbum KIM ,  Gyeom KIM ,  Dohee KIM ,  Dongwoo KIM ,  Seunghun LEE

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/04 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device includes a substrate including a fin-type active region, the fin-type active region extending in a first direction; a plurality of channel layers on the fin-type active region, the plurality of channel layers including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer isolated from direct contact with each other in a direction perpendicular to an upper surface of the substrate; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; a gate insulating film between the plurality of channel layers and the gate electrode; and source/drain regions electrically connected to the plurality of channel layers. In a cross section taken in the second direction, the uppermost channel layer has a width greater than a width of the intermediate channel layer.

公开(公告)号：US20220005946A1

公开(公告)日：2022-01-06

申请号：US17192301

申请日：2021-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun KIM ,  Dahye KIM ,  Jinbum KIM ,  Gyeom KIM ,  Dohee KIM ,  Dongwoo KIM ,  Seunghun LEE

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/417

Abstract: A semiconductor device includes a substrate including a fin-type active region, the fin-type active region extending in a first direction; a plurality of channel layers on the fin-type active region, the plurality of channel layers including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer isolated from direct contact with each other in a direction perpendicular to an upper surface of the substrate; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; a gate insulating film between the plurality of channel layers and the gate electrode; and source/drain regions electrically connected to the plurality of channel layers. In a cross section taken in the second direction, the uppermost channel layer has a width greater than a width of the intermediate channel layer.