公开(公告)号：US20230111854A1

公开(公告)日：2023-04-13

申请号：US17851245

申请日：2022-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JU-IL CHOI ,  UN-BYOUNG KANG ,  MINSEUNG YOON ,  YONGHOE CHO ,  JEONGGI JIN ,  YUN SEOK CHOI

IPC: H01L25/10 ,  H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48

Abstract: Provided is a semiconductor package, including a first redistribution substrate, a first semiconductor chip on the first redistribution substrate, first bumps between the first redistribution substrate and the first semiconductor chip, a conductive structure on the first redistribution substrate and spaced apart from the first semiconductor chip, a second redistribution substrate on the first semiconductor chip, second bumps between the first semiconductor chip and the second redistribution substrate, a second semiconductor chip on the second redistribution substrate, a first mold layer between the first redistribution substrate and the second redistribution substrate, and on the first semiconductor chip, and a second mold layer on the second redistribution substrate and the second semiconductor chip, and spaced apart from the first mold layer.

公开(公告)号：US20230103196A1

公开(公告)日：2023-03-30

申请号：US17740508

申请日：2022-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： GYUHO KANG ,  JONGHO PARK ,  SEONG-HOON BAE ,  JEONGGI JIN ,  JU-IL CHOI ,  ATSUSHI FUJISAKI

IPC: H01L23/48 ,  H01L25/10 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor device includes a first redistribution substrate, a semiconductor chip on a top surface of the first redistribution substrate, a conductive structure on the top surface of the first redistribution substrate and laterally spaced apart from the semiconductor chip, and a molding layer on the first redistribution substrate and covering a sidewall of the semiconductor chip and a sidewall of the conductive structure. The conductive structure includes a first conductive structure having a first sidewall, and a second conductive structure on a top surface of the first conductive structure and having a second sidewall. The first conductive structure has an undercut at a lower portion of the first sidewall. The second conductive structure has a protrusion at a lower portion of the second sidewall.

公开(公告)号：US20210090984A1

公开(公告)日：2021-03-25

申请号：US16830361

申请日：2020-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： JINHO CHUN ,  JIN HO AN ,  TEAHWA JEONG ,  JEONGGI JIN ,  JU-IL CHOI ,  ATSUSHI FUJISAKI

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48

Abstract: There are provided semiconductor packages including a redistribution substrate and a semiconductor chip mounted on the redistribution substrate. The redistribution substrate may include a lower protective layer, a first conductive pattern disposed on the lower protective layer, a first insulating layer surrounding the first conductive pattern and disposed on the lower protective layer, and a second insulating layer disposed on the first insulating layer. The first insulating layer may include a first upper surface that includes a first flat portion extending parallel to an upper surface of the lower protective layer, and a first recess facing the lower protective layer and in contact with the first conductive pattern. The first recess may be directly connected to the first conductive pattern.

公开(公告)号：US20240429176A1

公开(公告)日：2024-12-26

申请号：US18417494

申请日：2024-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： JU-IL CHOI ,  KWANGOK JEONG ,  JAEMOK JUNG ,  JEONGGI JIN ,  TAE OH HA ,  HONGSEO HEO

IPC: H01L23/544 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

Abstract: A semiconductor package including: a first redistribution structure; a semiconductor chip on the first redistribution structure; a pad insulation layer on a lower surface of the first redistribution structure; a conductive pad extending into a lower surface of the pad insulation layer and electrically connected to the first redistribution structure; and a plurality of alignment patterns on an edge of the pad insulation layer, each of the plurality of alignment patterns including a first portion extending into a lower surface of the pad insulation layer and a second portion extending away from the lower surface of the pad insulation layer.

公开(公告)号：US20220208703A1

公开(公告)日：2022-06-30

申请号：US17697830

申请日：2022-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： JU-IL CHOI ,  UN-BYOUNG KANG ,  JIN HO AN ,  JONGHO LEE ,  JEONGGI JIN ,  ATSUSHI FUJISAKI

IPC: H01L23/00

Abstract: Semiconductor devices are provided. A semiconductor device includes an insulating layer and a conductive element in the insulating layer. The semiconductor device includes a first barrier pattern in contact with a surface of the conductive element and a surface of the insulating layer. The semiconductor device includes a second barrier pattern on the first barrier pattern. Moreover, the semiconductor device includes a metal pattern on the second barrier pattern. Related semiconductor packages are also provided.

公开(公告)号：US20220157702A1

公开(公告)日：2022-05-19

申请号：US17381869

申请日：2021-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： JU-IL CHOI ,  GYUHO KANG ,  SEONG-HOON BAE ,  JIN HO AN ,  JEONGGI JIN ,  ATSUSHI FUJISAKI

IPC: H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor package may include a redistribution substrate, a semiconductor chip mounted on a top surface of the redistribution substrate, and a conductive terminal provided on a bottom surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern including a via portion in contact with the conductive terminal and a wire portion on the via portion and an insulating layer covering top and side surfaces of the under-bump pattern. A central portion of a bottom surface of the via portion may be provided at a level higher than an edge portion of the bottom surface of the via portion.

公开(公告)号：US20250125290A1

公开(公告)日：2025-04-17

申请号：US18647497

申请日：2024-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUNSU HWANG ,  JUMYONG PARK ,  DONGJOON OH ,  SANGHOO CHO ,  JEONGGI JIN

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor device includes a structure including a dielectric layer and a wire pattern embedded in the dielectric layer. The dielectric layer includes first regions and a second region around the first regions. The second region has an upper surface positioned at a lower level than upper surfaces of the first regions. A barrier layer is on the structure. The barrier layer is disposed on each first region among the first regions and is connected to the wire pattern. A seed metal layer is on the barrier layer. A conductive pad is on the seed metal layer.

公开(公告)号：US20230102285A1

公开(公告)日：2023-03-30

申请号：US18074134

申请日：2022-12-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGGI JIN ,  SOLJI SONG ,  TAEHWA JEONG ,  JINHO CHUN ,  JUIL CHOI ,  ATSUSHI FUJISAKI

IPC: H01L23/00 ,  H01L23/522

Abstract: A semiconductor package including a semiconductor chip, a redistribution layer structure disposed under the semiconductor chip, a bump pad disposed under the redistribution layer structure and having an upper structure of a first width and a lower structure of a second width less than the first width, a metal seed layer disposed along a lower surface of the upper structure and a side surface of the lower structure, an insulating layer surrounding the redistribution layer structure and the bump pad, and a bump structure disposed under the bump pad. A first undercut is disposed at one end of the metal seed layer that contacts the upper structure, and a second undercut is disposed at an other end of the metal seed layer that contacts the lower structure.

公开(公告)号：US20210305189A1

公开(公告)日：2021-09-30

申请号：US17088350

申请日：2020-11-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGGI JIN ,  SOLJI SONG ,  TAEHWA JEONG ,  JINHO CHUN ,  JUIL CHOI ,  ATSUSHI FUJISAKI

IPC: H01L23/00 ,  H01L23/522

Abstract: A semiconductor package including a semiconductor chip, a redistribution layer structure disposed under the semiconductor chip, a bump pad disposed under the redistribution layer structure and having an upper structure of a first width and a lower structure of a second width less than the first width, a metal seed layer disposed along a lower surface of the upper structure and a side surface of the lower structure, an insulating layer surrounding the redistribution layer structure and the bump pad, and a bump structure disposed under the bump pad. A first undercut is disposed at one end of the metal seed layer that contacts the upper structure, and a second undercut is disposed at an other end of the metal seed layer that contacts the lower structure.

公开(公告)号：US20250105116A1

公开(公告)日：2025-03-27

申请号：US18974377

申请日：2024-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： JU-IL CHOI ,  GYUHO KANG ,  SEONG-HOON BAE ,  JIN HO AN ,  JEONGGI JIN ,  ATSUSHI FUJISAKI

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor package may include a redistribution substrate, a semiconductor chip mounted on a top surface of the redistribution substrate, and a conductive terminal provided on a bottom surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern including a via portion in contact with the conductive terminal and a wire portion on the via portion and an insulating layer covering top and side surfaces of the under-bump pattern. A central portion of a bottom surface of the via portion may be provided at a level higher than an edge portion of the bottom surface of the via portion.