公开(公告)号：US20210193661A1

公开(公告)日：2021-06-24

申请号：US17032040

申请日：2020-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYUNGHWAN LEE ,  YONGSEOK KIM ,  HYUNCHEOL KIM ,  SATORU YAMADA ,  SUNGWON YOO ,  JAEHO HONG

IPC: H01L27/108 ,  G11C7/18

Abstract: Memory devices may include a source region, channels, a gate insulation layer pattern, a selection gate pattern, a first gate pattern, a second gate pattern and a drain region. The source region may include first impurities having a first conductivity type at an upper portion of a substrate. The channels may contact the source region. Each of the channels may extend in a vertical direction that is perpendicular to an upper surface of the substrate. The selection gate pattern may be on sidewalls of the channels. The first gate pattern may be on the sidewalls of the channels. The first gate pattern may be a common electrode of all of multiple channels. The second gate patterns may be on the sidewalls of the channels. The drain region may include second impurities having a second conductivity type that is different from the first conductivity type at an upper portion of each of the channels.

公开(公告)号：US20220367514A1

公开(公告)日：2022-11-17

申请号：US17671533

申请日：2022-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUNCHEOL KIM ,  YONGSEOK KIM ,  DONGSOO WOO ,  SUNGWON YOO ,  KYUNGHWAN LEE ,  JAEHO HONG

IPC: H01L27/11597 ,  H01L27/11587

Abstract: A semiconductor memory device may include a stack including word lines and interlayer insulating patterns alternatingly stacked on a substrate, the word lines being extended in a first direction parallel to a top surface of the substrate, semiconductor patterns crossing the word lines and having a long axis extended in a second direction parallel to the top surface of the substrate, data storage patterns respectively interposed between the semiconductor patterns and the word lines, the data storage patterns including a ferroelectric material, bit lines extended in a third direction perpendicular to the top surface of the substrate and spaced apart from each other in the first direction, each of the bit lines being in contact with first side surfaces of the semiconductor patterns spaced apart from each other in the third direction, and a source line in contact with second side surfaces of the semiconductor patterns.

公开(公告)号：US20220130856A1

公开(公告)日：2022-04-28

申请号：US17335763

申请日：2021-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUNCHEOL KIM ,  JAEHO HONG ,  YONGSEOK KIM ,  ILGWEON KIM ,  HYEOUNGWON SEO ,  SUNGWON YOO ,  KYUNGHWAN LEE

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L25/065 ,  G11C7/18 ,  G11C8/14

Abstract: A semiconductor memory device includes first conductive lines stacked in a first direction perpendicular to a top surface of a substrate, second conductive lines extending in the first direction and intersecting the first conductive lines, and memory cells provided at intersection points between the first conductive lines and the second conductive lines, respectively. Each of the memory cells includes a semiconductor pattern parallel to the top surface of the substrate, the semiconductor pattern including a source region having a first conductivity type, a drain region having a second conductivity type, and a channel region between the source region and the drain region, first and second gate electrodes surrounding the channel region of the semiconductor pattern, and a charge storage pattern between the semiconductor pattern and the first and second gate electrodes.

公开(公告)号：US20220108741A1

公开(公告)日：2022-04-07

申请号：US17362138

申请日：2021-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAEHO HONG ,  Hyuncheol Kim ,  Yongseok Kim ,  Iigweon Kim ,  Hyeongwon Seo ,  Sungwon Yoo ,  Kyunghwan Lee

IPC: G11C11/402 ,  H01L27/102 ,  H01L29/66 ,  H01L29/749

Abstract: A semiconductor memory device according to the present inventive concept includes: a semiconductor substrate; a common source semiconductor layer doped with impurities of a first conductivity type on the semiconductor substrate; a plurality of insulating layers and a plurality of word line structures alternately stacked on the common source semiconductor layer; and a memory cell dielectric layer penetrating the plurality of insulating layers and the plurality of word line structures and covering an internal wall of a channel hole extending in a vertical direction, and a memory cell structure filling the channel hole. The memory cell structure includes a channel layer, which has the memory cell dielectric layer thereon and fills at least a portion of the channel hole, and a drain layer covering an upper surface of the channel layer, doped with impurities of a second conductivity type, and filling some of an upper portion of the channel hole.