公开(公告)号：US09116631B2

公开(公告)日：2015-08-25

申请号：US14101934

申请日：2013-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinHyuck Choi ,  Il Park

IPC: G06F12/06 ,  G06F3/06 ,  G06F12/08 ,  G06F12/12 ,  G06F13/00

CPC classification number: G06F3/0647 ,  G06F12/08 ,  G06F12/12 ,  G06F2212/171 ,  G06F2212/214 ,  G06F2212/401

Abstract: A mobile device includes a storage configured to store data, a buffer memory configured to include a swap victim buffer area and a normal data area, and an application processor configured to select page data to be swapped from the normal data area and to perform a swapping operation on the selected page data. The swapping operation performs an instant swapping operation or a lazy swapping operation according to a data type of the selected page data.

Abstract translation: 移动设备包括被配置为存储数据的存储器，被配置为包括交换受害者缓冲区域和正常数据区域的缓冲存储器，以及应用处理器，被配置为选择要从正常数据区域进行交换的页面数据并执行交换 对所选页面数据进行操作。 交换操作根据所选页数据的数据类型执行即时交换操作或延迟交换操作。

公开(公告)号：US20150082000A1

公开(公告)日：2015-03-19

申请号：US14462774

申请日：2014-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min Hong ,  Sim Ji Lee ,  JaeYoung Hur ,  JiWoong Kwon ,  Il Park ,  Jong-Jin Lee ,  Jinyong Jung

IPC: G06F12/10 ,  G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/507 ,  G06F2212/6022 ,  G06F2212/654 ,  G06F2212/68 ,  G06F2212/681

Abstract: A memory management unit comprises an address translation unit that receives a memory access request as a virtual address and translates the virtual address to a physical address. A translation lookaside buffer stores page descriptors of a plurality of physical addresses, the address translation unit determining whether a page descriptor of a received virtual address is present in the translation lookaside buffer. A prefetch buffer stores page descriptors of the plurality of physical addresses. The address translation unit, in the event the page descriptor of the received virtual address is not present in the translation lookaside buffer, further determines whether the page descriptor of the received virtual address is present in the prefetch buffer; updates the translation lookaside buffer with the page descriptor in response to the determination; and performs a translation of the virtual address to a physical address using the page descriptor.

Abstract translation: 存储器管理单元包括地址转换单元，其接收作为虚拟地址的存储器访问请求并将虚拟地址转换为物理地址。 翻译后备缓冲器存储多个物理地址的页面描述符，地址转换单元确定所接收的虚拟地址的页面描述符是否存在于翻译后备缓冲器中。 预取缓冲器存储多个物理地址的页面描述符。 地址转换单元，在接收到的虚拟地址的页面描述符不存在于翻译后备缓冲器中的情况下，进一步确定接收的虚拟地址的页面描述符是否存在于预取缓冲器中; 响应于确定，用页面描述符更新翻译后备缓冲器; 并使用页面描述符执行虚拟地址到物理地址的转换。

公开(公告)号：US09645934B2

公开(公告)日：2017-05-09

申请号：US14462774

申请日：2014-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min Hong ,  Sim Ji Lee ,  JaeYoung Hur ,  JiWoong Kwon ,  Il Park ,  Jong-Jin Lee ,  Jinyong Jung

IPC: G06F12/10 ,  G06F12/08 ,  G06F12/0862 ,  G06F12/1009 ,  G06F12/1027

CPC classification number: G06F12/0862 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/507 ,  G06F2212/6022 ,  G06F2212/654 ,  G06F2212/68 ,  G06F2212/681

Abstract: A page descriptor can be stored in advance in a memory management unit under various conditions so that an address translation overhead can be reduced. The memory management unit comprises an address translation unit that receives a memory access request as a virtual address and translates the virtual address to a physical address. A translation lookaside buffer (TLB) stores page descriptors of a plurality of physical addresses, the address translation unit determining whether a page descriptor corresponding to a received virtual address is present in the translation lookaside buffer. A prefetch buffer stores page descriptors of the plurality of physical addresses. The address translation unit, in the event the page descriptor corresponding to the received virtual address is not present in the translation lookaside buffer, further determines whether the page descriptor corresponding to the received virtual address is present in the prefetch buffer; updates the translation lookaside buffer with the page descriptor corresponding to the received virtual address; and performs a translation of the virtual address to a physical address using the page descriptor corresponding to the received virtual address. The prefetch buffer may include sub-prefetch buffers, and may be updated based on access direction information.

公开(公告)号：US09606916B2

公开(公告)日：2017-03-28

申请号：US14307994

申请日：2014-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Hyun Lee ,  Jun Hee Yoo ,  Dongsoo Kang ,  Il Park ,  Kiyeon Lee ,  Euicheol Lim

IPC: G06F12/06

CPC classification number: G06F12/0607 ,  Y02D10/13

Abstract: A memory system includes a high-bandwidth memory device, the high-bandwidth memory device having a relatively high operation bandwidth, the high-bandwidth memory device having a plurality of access channels. A low-bandwidth memory device has a relatively low operation bandwidth relative to the high-bandwidth memory device, the low-bandwidth memory device having one or more access channels. An interleaving unit performs a memory interleave operation among the plurality of access channels of the high-bandwidth memory device and an access channel of the one or more access channels of the low-bandwidth memory device.

公开(公告)号：US09183149B2

公开(公告)日：2015-11-10

申请号：US13793023

申请日：2013-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Il Park ,  Young Pyo Joo

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0831

Abstract: A multiprocessor system includes a plurality of master devices, at least one slave device, and a system bus connecting the master devices to the at least one slave device. At least one of the master devices includes at least one cache memory, and the system bus processes a data write or data read request corresponding a transaction issued to the slave device from at least one of the master devices prior to termination of a snooping operation on the master devices.

Abstract translation: 多处理器系统包括多个主设备，至少一个从设备和将主设备连接到至少一个从设备的系统总线。 主设备中的至少一个包括至少一个高速缓冲存储器，并且系统总线在对窥探操作终止之前从至少一个主设备处理对应于从从设备发出的事务的数据写入或数据读取请求 主设备。