Electric stand
    1.
    外观设计

    公开(公告)号:USD993501S1

    公开(公告)日:2023-07-25

    申请号:US29796189

    申请日:2021-06-23

    Designer: Hyunsu Park

    Abstract: FIG. 1 is a front perspective view of an electric stand showing my new design;
    FIG. 2 is a front view thereof;
    FIG. 3 is a rear view thereof;
    FIG. 4 is a left-side view thereof;
    FIG. 5 is a right-side view thereof;
    FIG. 6 is a top view thereof; and,
    FIG. 7 is a bottom view thereof.
    The broken lines in the figures depict portions of the electric stand which form no part of the claimed design.

    Signal receiver and operation method thereof

    公开(公告)号:US11588453B2

    公开(公告)日:2023-02-21

    申请号:US17176239

    申请日:2021-02-16

    Abstract: A signal receiver includes a data sampler receiving a differential input signal having first and second input signals and determining bit values of the differential input signal based on first and second reference voltages, and a reference voltage generator performing a pre-tuning operation and a post-tuning operation to generate the reference voltages. The reference voltage generator performs the pre-tuning operation by generating first and second initial voltages and adjusting one of the initial voltages to generate third and fourth voltages. After the pre-tuning operation, the reference voltage generator performs the post-tuning operation by increasing or decreasing the third voltage to generate the first reference voltage and decreasing or increasing the fourth voltage to generate the second reference voltage based on a comparison result between the third voltage and the first input signal and a second comparison result between the fourth voltage and second input signal.

    Wireless charger
    3.
    外观设计

    公开(公告)号:USD991169S1

    公开(公告)日:2023-07-04

    申请号:US29796200

    申请日:2021-06-23

    Designer: Hyunsu Park

    Abstract: FIG. 1 is a front perspective view of a wireless charger showing my new design;
    FIG. 2 is a front view thereof;
    FIG. 3 is a rear view thereof;
    FIG. 4 is a left-side view thereof;
    FIG. 5 is a right-side view thereof;
    FIG. 6 is a top view thereof;
    FIG. 7 is a bottom view thereof; and,
    FIG. 8 is a rear perspective view thereof.
    The broken lines in the figures depict portions of the wireless charger which form no part of the claimed design.

    Wireless charger
    4.
    外观设计

    公开(公告)号:USD1018453S1

    公开(公告)日:2024-03-19

    申请号:US29796198

    申请日:2021-06-23

    Designer: Hyunsu Park

    Abstract: FIG. 1 is a front perspective view of a wireless charger showing my new design;
    FIG. 2 is a front view thereof;
    FIG. 3 is a rear view thereof;
    FIG. 4 is a left-side view thereof;
    FIG. 5 is a right-side view thereof;
    FIG. 6 is a top view thereof;
    FIG. 7 is a bottom view thereof; and,
    FIG. 8 is a bottom perspective view thereof.
    The broken lines in the figures depict portions of the wireless charger which form no part of the claimed design.

    Wine cooler
    5.
    外观设计

    公开(公告)号:USD994437S1

    公开(公告)日:2023-08-08

    申请号:US29796193

    申请日:2021-06-23

    Designer: Hyunsu Park

    Abstract: FIG. 1 is a front perspective view of a wine cooler showing my new design;
    FIG. 2 is a front view thereof;
    FIG. 3 is a rear view thereof;
    FIG. 4 is a left-side view thereof;
    FIG. 5 is a right-side view thereof;
    FIG. 6 is a top view thereof; and,
    FIG. 7 is a bottom view thereof.
    The broken lines in the figures depict portions of the wine cooler which form no part of the claimed design.

    Semiconductor device and memory system

    公开(公告)号:US12211572B2

    公开(公告)日:2025-01-28

    申请号:US17680425

    申请日:2022-02-25

    Abstract: A semiconductor device includes a multilevel receiver including a signal determiner receiving a plurality of multilevel signals and outputting a result of mutual comparison of the plurality of multilevel signals as an N-bit signal, where N is a natural number equal to or greater than 2. A decoder restores a valid signal among the N-bit signals from the signal determiner to an M-bit data signal, where M is a natural number less than N. A clock generator receives a reference clock signal, generates an input clock signal using the reference clock signal, inputs the input clock signal to the signal determiner, and determines a phase of the input clock signal based on an occurrence probability of an invalid signal not restored to the M-bit data signal among the N-bit signals.

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