Processor element matrix performing maximum/average pooling operations

    公开(公告)号:US11409694B2

    公开(公告)日:2022-08-09

    申请号:US16936965

    申请日:2020-07-23

    Abstract: A processor is provided. The processor includes a plurality of processing elements configured to be arranged in a matrix form, and a controller configured to control the plurality of processing elements during a plurality of cycles to process a target data, control first processing elements so that each of the first processing elements operates data provided from adjacent first processing elements and the input first element and inputs each of second elements included in a second row among the plurality of elements to second processing elements arranged in the second row among the plurality of processing elements, control the second processing elements so that each of the second processing elements operates data provided from adjacent second processing elements and the input second element, and operates data provided from the adjacent first processing elements in the same column among the first processing elements and pre-stored operation data.

    Storage device and memory controller thereof
    3.
    发明授权
    Storage device and memory controller thereof 有权
    存储设备及其存储器控制器

    公开(公告)号:US09049005B2

    公开(公告)日:2015-06-02

    申请号:US13674174

    申请日:2012-11-12

    Abstract: A memory controller controlling a nonvolatile memory is provided. The memory controller includes an encryption key feeder configured to feed a cipher key according to a logical address transferred from a host; and an encryption engine configured to perform an encryption operation on data transferred from the host or a decryption operation on data transferred from the nonvolatile memory device, using the cipher key provided from the encryption key feeder.

    Abstract translation: 提供控制非易失性存储器的存储器控​​制器。 存储器控制器包括:加密密钥进给器,配置为根据从主机传送的逻辑地址来提供加密密钥; 以及加密引擎,被配置为对从所述主机传送的数据执行加密操作或对从所述非易失性存储器件传送的数据进行解密操作,所述加密引擎使用从所述加密密钥馈送器提供的密码密钥。

    PLASMA TORCH AND PLASMA SCRUBBER APPARATUS INCLUDING THE SAME

    公开(公告)号:US20250048528A1

    公开(公告)日:2025-02-06

    申请号:US18427431

    申请日:2024-01-30

    Abstract: A plasma torch includes a cathode, a pilot electrode disposed on a first outer circumference of the cathode and separated from an exterior surface of the cathode, an electrode protection member disposed below the pilot electrode and including a first insulator, an anode disposed on a second outer circumference of a process space and disposed below the pilot electrode, and a discharge gas flow path coupled to a separation gap formed between the exterior surface of the cathode and an inner surface of the pilot electrode. The discharge gas flow path is configured to supply a discharge gas.

    Electronic device and data compression method thereof

    公开(公告)号:US11226738B2

    公开(公告)日:2022-01-18

    申请号:US15750733

    申请日:2016-08-04

    Abstract: Disclosed are an electronic device and a data compression method thereof. According to a data compression method of an electronic device of the present invention, the method comprises the steps of: compressing a page; determining whether data included in the compressed page is stored in a memory; and merging the compressed page with data previously stored in the memory when a result of the determination shows that the data included in the compressed page is the same as the previously stored data. Therefore, the electronic device can prevent a page including the same or similar data from being stored a multiple number of times in a swap area, thereby raising memory securing efficiency.

    Memory system performing error correction of address mapping table

    公开(公告)号:US10514981B2

    公开(公告)日:2019-12-24

    申请号:US15718143

    申请日:2017-09-28

    Abstract: A memory system includes a nonvolatile memory device, a dynamic random access memory (DRAM) configured to store an address mapping table for an access to the nonvolatile memory device, and a controller configured to store, in the DRAM, the address mapping table that is divided in units of address mapping data, each of the units having a size of an interface of the DRAM, read, from the stored address mapping table, target address mapping data corresponding to a logical address that is received from a host, the target address mapping data including a target parity and physical addresses of the nonvolatile memory device, and perform an error correction on the read target address mapping data, using the target parity.

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