公开(公告)号：US20220029095A1

公开(公告)日：2022-01-27

申请号：US17192093

申请日：2021-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuncheol KIM ,  Yongseok KIM ,  Hyeoungwon SEO ,  Sungwon YOO ,  Kyunghwan LEE ,  Jaeho HONG

IPC: H01L45/00 ,  H01L27/24 ,  H01L23/00

Abstract: A vertical variable resistance memory device including gate electrodes spaced apart from each other in a first direction on a substrate, each of the gate electrodes including graphene and extending in a second direction, the first direction being substantially perpendicular to an upper surface of the substrate and the second direction being substantially parallel to the upper surface of the substrate; first insulation patterns between the gate electrodes, each of the first insulation patterns including boron nitride (BN); and at least one pillar structure extending in the first direction through the gate electrodes and the first insulation patterns on the substrate, wherein the at least one pillar structure includes a vertical gate electrode extending in the first direction; and a variable resistance pattern on a sidewall of the vertical gate electrode.

公开(公告)号：US20250142806A1

公开(公告)日：2025-05-01

申请号：US19003119

申请日：2024-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan LEE ,  Yongseok KIM ,  Ilgweon KIM ,  Hyeoungwon SEO ,  Sungwon YOO ,  Jaeho HONG

IPC: H10B12/00

Abstract: A semiconductor memory device includes a word line extending in a vertical direction, a semiconductor pattern having a ring-shaped horizontal cross-section that extends around the word line, a bit line at a first end of the semiconductor pattern, and a capacitor structure at second end of the semiconductor pattern. The capacitor structure includes a lower electrode layer electrically connected to the second end of the semiconductor pattern, having a ring-shaped horizontal cross-section, and including a connector extending in the vertical direction. A first segment extends in a horizontal direction from an upper end of the connector, and a second segment extends in the horizontal direction from a lower end of the connector. An upper electrode layer surrounded by the lower electrode layer, extends in the vertical direction, and a capacitor dielectric layer is between the lower electrode layer and the upper electrode layer.

公开(公告)号：US20220352170A1

公开(公告)日：2022-11-03

申请号：US17725069

申请日：2022-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan LEE ,  Yongseok KIM ,  Ilgweon KIM ,  Hyeoungwon SEO ,  Sungwon YOO ,  Jaeho HONG

IPC: H01L27/108

Abstract: A semiconductor memory device includes a word line extending in a vertical direction, a semiconductor pattern having a ring-shaped horizontal cross-section that extends around the word line, a bit line disposed at a first end of the semiconductor pattern, and a capacitor structure disposed at second end of the semiconductor pattern. The capacitor structure includes a lower electrode layer electrically connected to the second end of the semiconductor pattern, having a ring-shaped horizontal cross-section, and including a connector extending in the vertical direction. A first segment extends in a horizontal direction from an upper end of the connector, and a second segment extends in the horizontal direction from a lower end of the connector. An upper electrode layer surrounded by the lower electrode layer, extends in the vertical direction, and a capacitor dielectric layer is between the lower electrode layer and the upper electrode layer.

公开(公告)号：US20220216239A1

公开(公告)日：2022-07-07

申请号：US17503713

申请日：2021-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungwon YOO ,  Yongseok KIM ,  Ilgweon KIM ,  Hyuncheol KIM ,  Hyeoungwon SEO ,  Kyunghwan LEE ,  Jaeho HONG

IPC: H01L27/12 ,  H01L27/13 ,  H01L25/065 ,  H01L25/18 ,  H01L21/84

Abstract: A semiconductor memory device is disclosed. The semiconductor memory device may include a data storage layer including data storage devices, an interconnection layer disposed on the data storage layer, and a selection element layer provided between the data storage layer and the interconnection layer. The interconnection layer may include bit lines extending in a first direction. The selection element layer may include a cell transistor connected between one of the data storage devices and one of the bit lines, and the cell transistor may include an active pattern and a word line, which crosses the active pattern and is extended in a second direction crossing the first direction.