公开(公告)号：US20230309289A1

公开(公告)日：2023-09-28

申请号：US18094719

申请日：2023-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungeun CHOI ,  KISEOK LEE ,  HAEJOON LEE ,  SEUNGJAE JUNG

IPC: H10B80/00 ,  H10B12/00

CPC classification number: H10B12/30 ,  H10B12/03 ,  H10B12/05 ,  H10B12/50 ,  H10B80/00

Abstract: A semiconductor memory device may include a lower layer including a first region and a second region, the lower layer extending in a first direction and a second direction perpendicular to the first direction, and a stack including word lines and interlayer insulating patterns, which are alternatingly stacked in a third direction perpendicular to the first direction and the second direction, the stack having a staircase structure on the second region. The word lines may extend from the first region to the second region in the first direction. Each of the word lines may include sub-gate electrodes, which extend parallel to each other in the first region, and a word line pad, which is connected in common to the sub-gate electrodes in the second region.